Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Where the title is not descriptive of the invention claimed, the examiner should require the substitution of a new title that is clearly indicative of the invention to which the claims are directed. Form paragraphs 6.11 and 6.11.01 may be used.
Drawings Objection
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a plurality of first conductive layers over the substrate, wherein the isolation layers and the first conductive layers are stacked alternatively; and a plurality of second conductive layers spaced apart from the first conductive layers, wherein the second conductive layers surround the capacitor dielectrics while the capacitor dielectrics surround the first capacitor electrode” in Claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 discloses each of the plurality of capacitors comprises a first capacitor electrode and a second capacitor electrode. Claim 1 also discloses a plurality of first conductive layers and a plurality of second conductive layers. It is unclear how to distinguish between first capacitor electrode and first conductive layer; and between second capacitor electrode second conductive layer. Claims 2-10 depend from Claim 1. For examination purpose, the Examiner interprets a plurality of first conductive layers and a plurality of second conductive layers are components different from first capacitor electrode and second capacitor electrode.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 4-10 rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Patent Pub. No. 2021/0257366) of record, in view of Yokuyama (U.S. Patent Pub. No. 2022/0246618) of record.
Regarding Claim 1
FIG. 12 (annotated below) of Lee discloses a semiconductor device, comprising: a substrate (LS); a plurality of capacitors (CAP) disposed on the substrate, wherein each of the capacitors extends along a first direction (D2), wherein each of the plurality of capacitors comprises a first capacitor electrode (PN), a second capacitor electrode (SN), and a capacitor dielectric (DE) separating the first capacitor electrode from the second capacitor electrode; a first space (SP1) on the substrate and extending along a second direction (D3) different from the first direction; and a plurality of isolation layers (ISO) each of which extends along the first direction, the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered (arranged so as to alternate on either side of a center) arrangement; a plurality of first conductive layers (WL) over the substrate, wherein the isolation layers and the first conductive layers are stacked alternatively; and a plurality of second conductive layers (PL) spaced apart from the first conductive layers, wherein the second conductive layers surround the capacitor dielectrics while the capacitor dielectrics surround the first capacitor electrode, wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first space is between the first surface and the second surface of the capacitor dielectric.
PNG
media_image1.png
584
676
media_image1.png
Greyscale
Lee is silent with respect to “a first supporting layer disposed on the substrate and extending along a second direction different from the first direction; and a plurality of isolation layers each of which extends along the first direction”.
FIG. 10 of Yokuyama discloses a similar semiconductor device, comprising: a substrate (1000); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction (D1), wherein each of the plurality of capacitors comprises a first capacitor electrode (1061), a second capacitor electrode (1056), and a capacitor dielectric (1063 between 861 and 856) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (1030-1) disposed on the substrate and extending along a second direction (D2) different from the first direction; a plurality of isolation layers (1030-2 to 1030-(N+1)) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered (arranged so as to alternate on either side of a center) arrangement; a plurality of first conductive layers (1098) over the substrate, wherein the isolation layers and the first conductive layers are stacked alternatively; and a plurality of second conductive layers (1040) spaced apart from the first conductive layers, wherein the second conductive layers surround the capacitor dielectrics while the capacitor dielectrics surround the first capacitor electrode, wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Yokuyama. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming vertical stacks with reduced size and capacitor cells with increased area ([0018] of Yokuyama).
Regarding Claim 2
FIG. 12 of Lee discloses the first supporting layer is in contact with the substrate, wherein the isolation layers are in contact with the capacitor dielectric, wherein each of the isolation layers (ISO) is spaced apart from the second conductive layer (PL) by the capacitor dielectric (DE), wherein the first conductive layers serve as the first capacitor electrodes while the second conductive layers serves as the second capacitor electrodes.
Regarding Claim 4
FIG. 1 of Yokuyama discloses a transistor electrically connected to one of the plurality of capacitors; and an interconnection trace disposed between the transistor and the one of the plurality of capacitors.
Regarding Claim 5
FIG. 1 of Yokuyama discloses the interconnection trace and the first capacitor electrode of the one of the plurality of capacitors are monolithic.
Regarding Claim 6
FIG. 1 of Yokuyama discloses the interconnection trace extends along the first direction (orthogonal to the surfaces of the capacitor electrodes) and serves as a portion of each of the first conductive layer, wherein the portions of the first conductive layer are spaced apart from each other by the isolation layers.
Regarding Claim 7
FIG. 2 of Yokuyama discloses the transistor comprises a word line (203) extending along a third direction (D3) different from the first direction and the second direction.
Regarding Claim 8
FIG. 12 of Lee discloses the transistor comprises a channel layer (ACT) spaced apart from the first capacitor electrode (SN) of the one of the plurality of capacitors by the word line (WL), wherein the channel layer is located at a horizontal level same as that of one of the first conductive layers.
Regarding Claim 9
FIG. 12 of Lee discloses a material of the channel layer (ACT, doped polysilicon [0048]) is different from a material of the first capacitor electrode (metal-base [0052]) of the one of the capacitors.
Regarding Claim 10
FIG. 2 of Yokuyama discloses the word line (203) is in contact with the substrate [0028].
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Lee and Yokuyama, in view of Wu (CN 111025845) of record.
Regarding Claim 3
Lee as modified by Yokuyama discloses Claim 2.
Lee as modified by Yokuyama is silent with respect to “a second supporting layer spaced apart from the first supporting layer and extending along the second direction, wherein the second supporting layer is in contact with the substrate; wherein the capacitor dielectrics and the second conductive layer have a ring-shaped profile”.
FIG. 11 of Wu discloses a similar semiconductor device, comprising a second supporting layer (left 111) spaced apart from the first supporting layer (right 111) and extending along the second direction, wherein the second supporting layer is in contact with the substrate (100); wherein the capacitor dielectrics (131) and the second conductive layer (132) have a ring-shaped profile.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Wu. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of improving the reliability of the finally prepared device (Abstract of Wu).
Pertinent Art
FIG. 21 of Li (U.S. Patent Pub. No. 2023/0389265) discloses a semiconductor device, comprising: a substrate (20); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction (D2), wherein (FIG. 9) each of the plurality of capacitors comprises a first capacitor electrode (301), a second capacitor electrode (303), and a capacitor dielectric (302) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (S1) disposed on the substrate and extending along a second direction (D3) different from the first direction; and a plurality of isolation layers (ISO) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric. FIG. 13 of Lugani (U.S. Patent Pub. No. 2014/0030863) discloses a semiconductor device, comprising: a substrate (12); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction, wherein each of the plurality of capacitors comprises a first capacitor electrode (34), a second capacitor electrode (46), and a capacitor dielectric (44) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (26) disposed on the substrate and extending along a second direction different from the first direction; and a plurality of isolation layers (54) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode. Pertinent art also includes Karda (U.S. Patent Pub. No. 2023/0022021), Kiehlbauch (U.S. Patent Pub. No. 2009/0176011), U.S. Patent Pub. No. 20230018716 and U.S. Patent Pub. No. 20220199621.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897