Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 2 rejected under 35 U.S.C. 103 as being unpatentable over Lee (DE 102018120840) of record, in view of Yang (U.S. Patent Pub. No. 2022/0302249) of record.
Regarding Claim 1
FIG. 16 of Lee discloses a semiconductor device, comprising: a substrate (100); a plurality of capacitors (DS) disposed on the substrate, wherein each of the capacitors extends along a first direction (D1), wherein each of the plurality of capacitors comprises a first capacitor electrode (EL1), a second capacitor electrode (EL2), and a capacitor dielectric (DL) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (first ILD1) disposed on the substrate and extending along a second direction (D2) different from the first direction; a second supporting layer (second ILD1) spaced apart from the first supporting layer and extending along the second direction; and a plurality of isolation layers (ILD2) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric; wherein the first supporting layer and the second supporting layer are disposed between the substrate and one of the first capacitor electrodes and are in direct contact with the substrate and one of the first capacitor electrodes; wherein the first supporting layer and the second supporting layer are separated by the second capacitor electrode and are in direct contact with the capacitor dielectric; wherein at least one of the capacitor dielectrics is sandwiched between and in direct contact with the substrate and one of first capacitor electrodes; wherein at least one of the capacitor dielectrics is sandwiched between and in direct contact with two of first capacitor electrodes; wherein the second capacitor electrode is spaced apart from the first capacitor electrodes by the capacitor dielectric.
Lee is silent with respect to “the first supporting layer surrounds the first capacitor electrode”.
FIG. 8 of Yang discloses a similar semiconductor device, comprising: a substrate (21); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction, wherein each of the plurality of capacitors comprises a first capacitor electrode (26), a second capacitor electrode (28), and a capacitor dielectric (27) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (first 231) disposed on the substrate and extending along a second direction different from the first direction; a second supporting layer (second 231) spaced apart from the first supporting layer and extending along the second direction; and a plurality of isolation layers (232) each of which extends along the first direction; wherein the first supporting layer surrounds the first capacitor electrode; wherein the first supporting layer and the second supporting layer are disposed between the substrate and one of the first capacitor electrodes and are in direct contact with the substrate and one of the first capacitor electrodes.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Yang. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of improving structural stability and capacitance ([0005] of Yang).
Regarding Claim 2
FIG. 8 of Yang discloses the isolation layers are in contact with the capacitor dielectric (27) and are in contact with the first capacitor electrode (26).
Claims 3-6 rejected under 35 U.S.C. 103 as being unpatentable over Lee and Yang, in view of Yokuyama (U.S. Patent Pub. No. 2022/0246618) of record.
Regarding Claim 3
Lee as modified by Yang discloses Claim 2.
Lee as modified by Yang is silent with respect to “the capacitor dielectrics and the second conductive layer have a ring-shaped profile” “the second capacitor electrodes surround the capacitor dielectrics while the capacitor dielectrics surround the first capacitor electrodes”.
FIG. 1 of Yokuyama discloses a similar semiconductor device, wherein the capacitor dielectrics and the second conductive layer have a ring-shaped profile; the second capacitor electrodes (1061) surround the capacitor dielectrics (1063) while the capacitor dielectrics surround the first capacitor electrodes (1056).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Yokuyama. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of forming vertical stacks with reduced size and capacitor cells with increased area ([0018] of Yokuyama).
Regarding Claim 4
FIG. 1 of Yokuyama discloses a transistor electrically connected to one of the plurality of capacitors; and an interconnection trace disposed between the transistor and the one of the plurality of capacitors.
Regarding Claim 5
FIG. 1 of Yokuyama discloses the interconnection trace and the first capacitor electrode of the one of the plurality of capacitors are monolithic.
Regarding Claim 6
FIG. 1 of Yokuyama discloses the interconnection trace extends along the first direction (orthogonal to the surfaces of the capacitor electrodes), wherein the transistor is electrically connected to the capacitors by the interconnection trace.
Claims 7-10 rejected under 35 U.S.C. 103 as being unpatentable over Lee and Yang, in view of Kim (KR 102967100, KR 20220050615, machine-translation provided).
Regarding Claim 7
Lee as modified by Yang and Yokuyama discloses Claim 4, wherein the transistor comprises a word line (203) extending along a third direction (D3) different from the first direction and the second direction.
Lee as modified by Yang and Yokuyama is silent with respect to “a height of the word line is equal to an overall height of the first capacitor electrodes and the isolation layers”.
FIG. 17 of Kim discloses a similar semiconductor device, wherein a height of the word line (32) is equal to an overall height of the first capacitor electrodes and the isolation layers.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Kim. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of providing a highly integrated memory cell (Abstract of Kim).
Regarding Claim 8
FIG. 17 of Kim discloses the transistor comprises a channel layer (25) spaced apart from the first capacitor electrode (36) of the one of the plurality of capacitors by the word line (32), wherein the channel layer is located at a horizontal level same as that of one of the first capacitor electrodes, wherein the word line is disposed between the bit line and the capacitors, wherein the word line is disposed over the isolation layers, wherein the bit line (26) is electrically connected to the channel layer.
Regarding Claim 9
FIG. 12 of Lee discloses a material of the channel layer (CH) is different from a material of the first capacitor electrode of the one of the capacitors.
Regarding Claim 10
FIG. 2 of Yokuyama discloses the word line (203) is in contact with the substrate [0028].
Claim 1 rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Li (U.S. Patent Pub. No. 2023/0389265) of record.
Regarding Claim 1
FIG. 16 of Lee discloses a semiconductor device, comprising: a substrate (100); a plurality of capacitors (DS) disposed on the substrate, wherein each of the capacitors extends along a first direction (D1), wherein each of the plurality of capacitors comprises a first capacitor electrode (EL1), a second capacitor electrode (EL2), and a capacitor dielectric (DL) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (first ILD1) disposed on the substrate and extending along a second direction (D2) different from the first direction; a second supporting layer (second ILD1) spaced apart from the first supporting layer and extending along the second direction; and a plurality of isolation layers (ILD2) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric; wherein the first supporting layer and the second supporting layer are disposed between the substrate and one of the first capacitor electrodes and are in direct contact with the substrate and one of the first capacitor electrodes; wherein the first supporting layer and the second supporting layer are separated by the second capacitor electrode and are in direct contact with the capacitor dielectric; wherein at least one of the capacitor dielectrics is sandwiched between and in direct contact with the substrate and one of first capacitor electrodes; wherein at least one of the capacitor dielectrics is sandwiched between and in direct contact with two of first capacitor electrodes; wherein the second capacitor electrode is spaced apart from the first capacitor electrodes by the capacitor dielectric.
Lee is silent with respect to “the first supporting layer surrounds the first capacitor electrode”.
FIG. 21 of Li discloses a similar semiconductor device, comprising: a substrate (20); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction (D2), wherein (FIG. 9) each of the plurality of capacitors comprises a first capacitor electrode (301), a second capacitor electrode (303), and a capacitor dielectric (302) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (27) disposed on the substrate and extending along a second direction (D3) different from the first direction; and a plurality of isolation layers (ISO) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode, and the first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric, and wherein the first supporting layer surrounds the first capacitor electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Li. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of improving the performance of the semiconductor structure ([0005] of Li).
Pertinent Art
FIG. 13 of Lugani (U.S. Patent Pub. No. 2014/0030863) discloses a semiconductor device, comprising: a substrate (12); a plurality of capacitors disposed on the substrate, wherein each of the capacitors extends along a first direction, wherein each of the plurality of capacitors comprises a first capacitor electrode (34), a second capacitor electrode (46), and a capacitor dielectric (44) separating the first capacitor electrode from the second capacitor electrode; a first supporting layer (26) disposed on the substrate and extending along a second direction different from the first direction; and a plurality of isolation layers (54) each of which extends along the first direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement; wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate; wherein the capacitor dielectric comprises a first surface and a second surface which are disposed on two opposite sides of the capacitor dielectric along the first direction, the second surface is exposed by the first capacitor electrode. Pertinent art also includes Karda (U.S. Patent Pub. No. 2023/0022021), Kiehlbauch (U.S. Patent Pub. No. 2009/0176011), U.S. Patent Pub. No. 20230018716, U.S. Patent Pub. No. 20220199621, U.S. Patent Pub. No. 20220310614, U.S. Patent Pub. No. 20230268379, CN 111025845, CN 107910327, WO 2022198884.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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