CTNF 18/223,168 CTNF 69045 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Information Disclosure Statement Applicant’s IDS submitted on 5/6/26 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record. Specification 07-29 AIA The disclosure is objected to because of the following informalities: In paragraph [0044] Figures 2 to 43 are referred to as cross-sectional views. Figures 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41 appear to be top views where the other figure are cross-sectional views taken along A-A' and B-B' lines in Figures 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41 . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 2 : Claim 1 recites “the spacer includes a first bridging portion extending laterally between two of the plurality of protruding portions.” Claim 2 which depends from claim 1 recites “the first bridging portion of the spacer is disposed between two of the plurality of first strip portions of the core.” These limitation place the first bridging portion in two different regions making the bridging region unclear. For purposes of examination the claim 2 has been interpreted as the bridging region further incudes the region between two strips. 07-34-01 Claims 7 and 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regrading claim 7: Claim 7 recites that a width is substantially less that another width. However, there is no guidance on what constitutes “substantially less” in the specification, nor have any examples with dimensions been given in the specification. Therefore the term “substantially” renders claim 7 indefinite, since one of ordinary skill would be unable to determine what would be substantially less than a given width from the disclosure. For purposes of examination substantially less has been interpreted to mean less. Regrading claim 8: Claim 8 recites etch rates that are substantially different. No etchant nor etch rate has been disclosed in the specification that could give guidance on what difference substantially different would mean, therefore this term is unclear. For purposes of examination substantially different has been interpreted to mean different. Regrading claim 9: Claim 9 recites etch rates that are substantially greater. No etchant nor etch rate has been disclosed in the specification that could give guidance on what difference substantially greater would mean, therefore this term is unclear. For purposes of examination substantially greater has been interpreted to mean greater. Regrading claim 10: Claim 10 recites etch rates that is substantially less. No etchant nor etch rate has been disclosed in the specification that could give guidance on what difference substantially less would mean, therefore this term is unclear. For purposes of examination substantially less has been interpreted to mean less. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-4, 6-8, and 11-13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 8, 12 of copending Application No. 17/969558 in view of Lin et al., US 20230068794 A1, hereafter Lin. A table comparing the claims of the instant application (US 18/223168) are to those of claims of 17/969558. The difference between the instant claims and those of application (US 18/223168) are underlined in the comparison table. Application 18/223168 Application 17/969558 1. A method of manufacturing a memory device, comprising: 1. A method of manufacturing a memory device, comprising: providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; providing a semiconductor substrate defined with an active area disposed over or in the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a first hard mask over the semiconductor substrate; forming a core over the first hard mask, wherein the core has a plurality of first strip portions and a plurality of protruding portions protruding laterally from a corresponding one of the plurality of the first strip portions; forming a core over the first hard mask, wherein the core has a strip portion and a protruding portion protruding laterally from the strip portion; forming a spacer surrounding the core, wherein the spacer includes a first bridging portion extending laterally between two of the plurality of protruding portions; forming a spacer surrounding the core; removing the plurality of first strip portions of the core; removing the strip portion of the core; removing portions of the first hard mask exposed through the spacer and the plurality of protruding portions of the core; removing portions of the first hard mask exposed through the spacer and the protruding portion of the core; forming a second hard mask surrounding the first hard mask; forming a second hard mask surrounding the first hard mask; removing the first hard mask; removing the first hard mask; removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area. removing portions of the semiconductor substrate exposed through the second hard mask to form a trench surrounding the active area. 3. The method according to claim 1, wherein after the formation of the spacer, the spacer has a recess laterally indented into the first bridging portion of the spacer. 8. The method according to claim 1, wherein after the formation of the spacer, the spacer has a recess laterally indented into the spacer. 8. The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially different from a second etch rate of the second hard mask relative to the etchant. 12. The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially different from a second etch rate of the second hard mask relative to the etchant. Regarding claim 1: The instant claims contain additional limitations requiring the forming of a plurality of strip regions and protrusion portions, while those of application 18/223168 form a single stripe region and protrusion region. Lin (Figure 16A, memory region MR) discloses that when forming memory devices forming multiple devices is desirable and doing so requires forming more than one stripe region, and that isolation regions can connect between stripes, creating isolating regions for devices. It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Lin to the method of copending application 17/969558 and to therefore formed a plurality of first strip regions and protruding portions. Do so would be analogous to duplication of parts MPEP 2144.04 and would form more than one memory device region, therefore allowing more than one isolated device to be formed on the wafer. Regarding claim 2: The method according to claim 1, wherein the first bridging portion of the spacer is disposed between two of the plurality of first strip portions of the core (Application 17/969558 does not specifically claim a bridging portion between the stripes, however, the spacer of 17/969558 is deposited over the strips and would therefore form spacer between the strips). Regarding claim 3: The method according to claim 1, wherein after the formation of the spacer, the spacer has a recess laterally indented into the first bridging portion of the spacer ( Application 17/969558 claims forming a spacer which is indented laterally into the spacer, but fails to claim the indentation in a first bridging portion. The bridging portion is the portion between two protruding portions. In the combination of Application 17/969558 there would be a bridging portion filing the region between the protrusion portion, which would then have the indentation since the region filled is between two higher regions). Regarding claim 4: The method according to claim 3, wherein the first bridging portion of the spacer is conformal to the recess of the spacer (Application 17/969558 claims forming a spacer over the core layer, which has stripe, but claim what that looks like. Lin, Figure 10 shows, that depositing a layer (Lin, Figure 10, 220) over a layer with strips forms layer that is conformal over the structure). Regarding claim 6: The method according to claim 1, wherein after the removal of the portions of the first hard mask exposed through the spacer and the plurality of protruding portions of the core, the first hard mask includes a second bridging portion extending laterally between two of a plurality of second strip portions of the first hard mask (Application 17/969558 does not specifically claim a second bridging portion between the stripes, however, the spacer of 17/969558 is deposited over the strips and would therefore form spacer between the strips). Regarding claim 7: The method according to claim 6, wherein a width of the first bridging portion is substantially less than a width of the second bridging portion (Application 17/969558 does not specifically claim a second bridging portion between the stripes, however, the spacer of 17/969558 is deposited over the strips and would therefore form spacer between the strips. Because the width between strips is larger that the width between protrusion parts the width of the first bridge would be less than the bridge width of the second bridge) . Regarding claim 8: The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially different from a second etch rate of the second hard mask relative to the etchant (This claim language is identical to claim 12 of Application 17/969558, which also depends from claim 1). Regarding claim 11, the combination of Application 17/969558 and Lin The method according to claim 1, wherein the second hard mask includes a plurality of strips separated from each other (Application 17/969558 in view of Lin discloses a plurality of parallel strips separated from each other so that isolated devices can be formed). Regarding claim 12, the combination of Application 17/969558 and Lin The method according to claim 11, wherein the plurality of strips are parallel to each other (Application 17/969558 in view of Lin discloses a plurality of parallel strips separated from each other so that isolated devices can be formed). Regarding claim 13, the combination of Application 17/969558 and Lin The method according to claim 11, wherein the plurality of strips have a same length (Application 17/969558 in view of Lin discloses a plurality of parallel strips separated from each other so that isolated devices can be formed, the total length of the strips is the same). Claim 5 and 9-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 17/969558 and Lin as applied to claim 1 above, and further in view of Chen et al., US 20190067008 A1, hereafter Chen. Regarding claim 5, Application 17/969558 and Lin fail to disclose: The method according to claim 1, wherein the second hard mask is formed by disposing a second hard mask material over the first hard mask, and planarizing the second hard mask material to expose the first hard mask . Chen discloses the following limitations: The method according to claim 1, wherein the second hard mask is formed by disposing a second hard mask material over the first hard mask, and planarizing the second hard mask material to expose the first hard mask (Chen, Figure 12-17 discloses a process where a first mask (210) is deposited and then a second mask (212) is deposited and planarized so that the top of the first mask is exposed, then both the first mask and the second mask are used to etch the layers below). It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have used planarization in the process of 17/969558 because the planarization process is known to allow multiple mask layer to be used to achieve smaller resolution than what is possible with a single mask layer. Regarding claim 9, Application 17/969558 and Lin fail to disclose: The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially greater than a second etch rate of the second hard mask relative to the etchant. Chen discloses the following limitations: The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially greater than a second etch rate of the second hard mask relative to the etchant (Chen [0079] discloses that first mask layer can be TiO x and second mask layer can be ZrO x or WO- x. ). It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have used different materials for the first mask and second mask as taught by Chen. Doing so would allow preferential etching of one material over the other and necessarily means that there is an etchant that will etch the first mask material at a greater rate than the second mask material. Regarding claim 10: The method according to claim 1, wherein a first etch rate of the first hard mask relative to an etchant is substantially less than a second etch rate of the second hard mask relative to the etchant (Chen [0079] discloses that first mask layer can be TiO x and second mask layer can be ZrO x or WO- x ). It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have used different materials for the first mask and second mask as taught by Chen. Doing so would allow preferential etching of one material over the other and necessarily means that there is an etchant that will etch the first mask material at a slower rate than the second mask material. Claim 14 and 15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 17/969558 and Lin as applied to claim 1 above, and further in view of Singhal et al. US 20230238238, hereafter Singhal. Regarding claim 14, Application No. 17/969558 in view of Lin fail to teach: The method according to claim 1, wherein the core includes photoresist material. Singhal discloses the following limitations: the core includes photoresist material (Singhal, Figure 1A-1C, core 101, and [0079] disclose the photoresist for the core). It would have obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Singhal to the process of Application 17/696558 and to therefore have used photoresist as the core material. The use of photoresist as a core material in a masking layer is taught by Singhal and would result in a core material with well-known properties that can be easily applied and patterned at low temperatures, and would therefore simplify the manufacturing process. Regarding claim 15, Application No. 17/969558 in view of Lin fail to teach: The method according to claim 1, wherein the spacer includes nitride. Singhal discloses the following limitations: the spacer includes nitride (Singhal, Figure 1A-1C, spacer 119 and [0076] discloses the silicon nitride for the spacer material). It would have obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Singhal to the process of Application 17/696558 and to therefore have used silicon nitride as the spacer material. The use of silicon nitride as a spacer is taught by Singhal and would result spacers with well-known properties that can be easily applied and patterned, and simplify the manufacturing process. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bei, US 20190096692 A1, discloses a multi-step process to improve the resolution of a mask. Chou et al., US 20220108894 A1, discloses a multi-step process to improve mask resolution and form island regions. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LINDA J. FLECK/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/223,168 Page 2 Art Unit: 2812 Application/Control Number: 18/223,168 Page 3 Art Unit: 2812 Application/Control Number: 18/223,168 Page 4 Art Unit: 2812 Application/Control Number: 18/223,168 Page 5 Art Unit: 2812 Application/Control Number: 18/223,168 Page 6 Art Unit: 2812 Application/Control Number: 18/223,168 Page 7 Art Unit: 2812 Application/Control Number: 18/223,168 Page 8 Art Unit: 2812 Application/Control Number: 18/223,168 Page 9 Art Unit: 2812 Application/Control Number: 18/223,168 Page 10 Art Unit: 2812 Application/Control Number: 18/223,168 Page 11 Art Unit: 2812 Application/Control Number: 18/223,168 Page 12 Art Unit: 2812 Application/Control Number: 18/223,168 Page 13 Art Unit: 2812 Application/Control Number: 18/223,168 Page 14 Art Unit: 2812
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