Attorney Docket Number: USP-NT455
Filing Date: 7/18/2023 (EFD of 10/26/2022 – DIV of Parent App 17/973,641)
Inventor: Yang
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the RCE amendments filed on 2/24/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/24/2026 has been entered.
Amendment Status
The submission filed on 2/24/2026 as an RCE amendment in reply to the Office action mailed on
1/28/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant amended claims 1-2, 4-8, and 10-14. Accordingly, pending in this Office action are claims 1-15. New grounds of rejection are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Objections
Claim 4 is objected to because of the following informalities: “…further has a main portion…” is improper, as the limitation “…a main portion…” was already recited within independent claim 1. For the purposes of examination, the “…a main portion…” of claim 4 will be construed to recite “…the main portion…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 2, 4, and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "…the first surface…" in line 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “…the first surface…” will be construed to recite “…the top surface…”.
Claim 4 recites the limitation "…the second surface…" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “…the second surface…” will be construed to recite “…the bottom surface…”.
Claim 11 recites the limitation "…the bump…" in line 15. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “…the bump…” will be construed to recite “…the at least one bump…”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20110062577 A1) in view of Chen (US 20080042255 A1) further in view of Kim (US 20050208707 A1).
Regarding claim 1, Hung (see, e.g., fig. 4) shows most aspects of the instant invention including a package structure comprising:
a substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”) having a bottom surface (e.g., bottom surface of first board part 314) and a top surface (e.g., top surface of first board part 314), including a patterned circuit layer (e.g., first trace 320 + external pad 326) and defining a through hole (e.g., central slot 313), wherein the patterned circuit layer (e.g., first trace 320 + external pad 326) comprises a conductive trace (e.g., first trace 320) and a bonding pad (e.g., external pad 326), wherein an extending portion (e.g., suspended inner lead 321 extension) of the conductive trace (e.g., first trace 320) of the patterned circuit layer (e.g., first trace 320) extends along a sidewall of the through hole (e.g., central slot 313), wherein the bonding pad (e.g., external pad 326) is formed on the bottom surface (e.g., bottom surface of first board part 314) of the substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”), wherein a main portion (see, e.g., annotated fig. 1) of the conductive trace (e.g., first trace 320) is formed on the bottom surface of the substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”) and is electrically connected to the bonding pad (e.g., external pad 326);
an electronic component (e.g., chip 10) having an active surface (e.g., active surface 11) over the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300), wherein the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is electrically connected to the patterned circuit layer (e.g., first trace 320) of the substrate (e.g., substrate 300, comprised of first board part 314 + second board part 315) through the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320 + external pad 326) in the through hole (e.g., central slot 313);
a package body (e.g., encapsulant 40) disposed in the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300) and encapsulating the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320), wherein the package body (e.g., encapsulant 40) contacts the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10);
wherein the electronic component (e.g., chip 10) comprises at least one bump (e.g., bonding pad 12) disposed on and protruded from the active surface (e.g., active surface 11) thereof, and an adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”) disposed on the active surface (e.g., active surface 11), wherein the extending portion (e.g., suspended inner lead 321 extension) of the conductive trace (e.g., first trace 320) of the patterned circuit layer (e.g., first trace 320 + external pad 326) is bent into the through hole (e.g., central slot 313) through the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”) and is connected to the at least one bump (e.g., bonding pad 12) of the electronic component (e.g., chip 10);
wherein the electronic component (e.g., chip 10) is attached to the top surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”) via the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”).
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Annotated fig. 1
Hung (see, e.g., fig. 4), however, fails to show the at least one bump is disposed on and protruded from the active surface thereof toward the through hole of the substrate and the at least one bump is surrounded by the adhesion layer, and that the extending portion of the conductive trace patterned circuit layer is not in direct contact with the active surface of the electronic component, while it also fails to show wherein the adhesion layer is extended from the first portion of the active surface to a periphery of the electronic component, such that a lateral surface of the electronic component is aligned with a lateral surface of the adhesion layer.
Chen (see, e.g., figs. 2G-1 – 2G-2), in a similar device to Hung, teaches an at least one bump (e.g., connecting pad 52) disposed on and protruded from an active surface (e.g., active surface 42) thereof toward a through hole (e.g., opening between substrate 10) of a substrate (e.g., substrate 10), and an extending portion (e.g., wire 50) is not in direct contact (see, e.g., connecting pad 52 physically separating the active surface from the wire) with the active surface (e.g., active surface 42) of an electronic component (e.g., chip 40).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the pad protrusion configuration (extending out of the electronic component and protruding toward the through hole, as opposed to protruding inward) of Chen within the setup of Hung, in order to achieve the expected result of increasing the potential space within the electronic component for other components as necessary, while simultaneously reducing the wire length required to enable the connectivity requirements within the device. Note that configuring the pad in this manner would leave it directly surrounded by the elastomer/adhesion layers.
Hung in view of Chen, however, fails to teach wherein the adhesion layer is extended from the first portion of the active surface to a periphery of the electronic component, such that a lateral surface of the electronic component is aligned with a lateral surface of the adhesion layer.
Kim (see, e.g., fig. 1E), in a similar device to Hung in view of Chen, teaches wherein an adhesion layer (e.g., adhesive 22) is extended from the first portion of an active surface (e.g., surface of chip 21 connected to bonding wires 23) to a periphery of an electronic component (e.g., chip 21) such that a lateral surface of the electronic component (e.g., chip 21) is aligned (e.g., note adhesive 22 and chip 21 are laterally aligned, see fig. 1E) with a lateral surface of the adhesion layer (e.g., adhesive 22).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the lateral alignment configuration of Kim within the chip and adhesion layer configuration of Hung in view of Chen, in order to achieve the expected result of reducing the cost of material of the adhesion layer while manufacturing the device, while simultaneously providing a full adhesive interface between the chip and the substrate.
Regarding claim 2, Hung (see, e.g., fig. 4) shows wherein the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) has a first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) and a second portion (e.g., portion of active surface 11 directly in contact with elastomer 350), wherein the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”) is provided on the second portion (e.g., portion of active surface 11 directly in contact with elastomer 350) of the active surface (e.g., active surface 11), wherein the first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is exposed in the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300), and the second portion (e.g., portion of active surface 11 directly in contact with elastomer 350) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is adhered to the top surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300) through the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”).
Regarding claim 3, Hung (see, e.g., fig. 4) shows wherein the second portion (e.g., portion of active surface 11 directly in contact with elastomer 350) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) surrounds the first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10).
Regarding claim 4, Hung (see, e.g., fig. 4) shows wherein the patterned circuit layer (e.g., first trace 320 + external pad 326) is disposed adjacent to the second surface (e.g., bottom surface of first board part 314) of the substrate (e.g., substrate 300), wherein the patterned circuit layer (e.g., first trace 320 + external pad 326) further has the main portion (see, e.g., annotated fig. 1 above) disposed on the second surface (e.g., bottom surface of first board part 314) of the substrate (e.g., substrate 300) and integrally extended to the extending portion (e.g., suspended inner lead 321 extension), wherein the package body (e.g., encapsulant 40) not only encapsulates the extending portion (e.g., suspended inner lead 321 extension) of the conductive trace (e.g., first trace 320) of the patterned circuit layer (e.g., first trace 320 + external pad 326) but also is in contact with the main portion (see, e.g., annotated fig. 1 above) thereof.
Regarding claim 5, Hung (see, e.g., fig. 4) shows wherein the package body (e.g., encapsulant 40) is further disposed on the top surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300) and encapsulating the electronic component (e.g., chip 10).
Regarding claim 6, Hung (see, e.g., fig. 4) shows a width of the main portion (see, e.g., annotated fig. 1 above) of the conductive trace (e.g., first trace 320) is larger than a width of the bonding pad (e.g., external pad 326), wherein a width of the main portion (see, e.g., annotated fig. 1 above) of the conductive trace (e.g., first trace 320) is larger than a width (see, e.g., fig. 4, also note the integral dynamic of the main portion and bonding pad of the instant app are drawn substantially similarly to fig. 4, see the main portion of annotated fig. 1 v.s. the external pad 326) of the bonding pad (e.g., external pad 326).
Regarding claim 7, Hung (see, e.g., fig. 4) shows wherein the extending portion (e.g., suspended inner lead 321 extension) of the conductive trace (e.g., first trace 320) of the patterned circuit layer (e.g., first trace 320 + external pad 326) and the patterned circuit layer (e.g., first trace 320 + external pad 326) and the bonding pad (e.g., external pad 326) are formed integrally (see, e.g., paragraph 25 “The inner lead 321 integrally connects with the first trace 320”, also note first trace 320 and external pad 326 are integrally attached, see fig. 4).
Regarding claim 8, Hung (see, e.g., fig. 4) shows at least one external connector (e.g., external terminals 50) disposed on the bonding pad (e.g., external pad 326) of the patterned circuit layer (e.g., first trace 320 + external pad 326).
Regarding claim 10, Hung (see, e.g., fig. 4) shows wherein a length of the extending portion (e.g., suspended inner lead 321 extension) of the conductive trace (e.g., first trace 320) of the patterned circuit layer (e.g., first trace 320 + external pad 326) is greater than a thickness (e.g., note that the first trace 320 extends from below the bottom surface of first board 314 above the top surface of first board 314, so the length of the first trace 320 is greater than the first board 314’s thickness) of the substrate (e.g., substrate 300).
Chen (see, e.g., fig. 2G-2) teaches wherein a thickness of the adhesion layer (e.g., adhesive element 30) is greater than a height of the at least one bump (e.g., connecting pad 52), such that the at least one bump (e.g., connecting pad 52) is surrounded by the adhesion layer (e.g., adhesive element 30) toward the through hole of the substrate (e.g., substrate 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness configuration of Chen within the device of Hung in view of Chen further in view of Kim, in order to achieve the expected result of reducing the size of thickness of the at least one bump, thus reducing the cost of material manufacturing within the device, as well as increasing the extension depth of the wires within the through hole configuration, providing additional room within the through hole area, as opposed to large-thickness bumps protruding substantially out of the through hole region (also note the depth of the through hole region is substantially affected by the thickness of the adhesion layer). In addition, also note that the bump of Hung within fig. 4 is drawn to be substantially smaller in thickness than the adhesion layer, and it would have been obvious to one of ordinary skill in the art at the time of filing the invention to optimize the size of the pads for space within the through hole region as necessary.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view Chen further in view of Kim and Li (US 20170103957 A1).
Regarding claim 9, Hung in view of Chen further in view of Kim fails to teach the patterned circuit layer is formed from a metal foil.
Li (see, e.g., fig 1), in a similar device, to Hung in view of Chen further in view of Kim, teaches a patterned circuit layer formed from a metal foil (see, e.g., paragraph 20 “The metal foil 108 is etched in a pattern to create metal traces…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the patterned circuit layer of Hung in view of Chen further in view of Kim from the metal foil of Li, to achieve the expected result of providing conductive properties within the layer in order to allow the transfer of current as necessary between the electronic component and the substrate/external terminals.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Chen further in view of Kim and Kang (US 20150270229 A1).
Regarding claim 11, Hung (see, e.g., fig. 4) shows most aspects of the instant invention, including a method of manufacturing a package structure comprising:
Providing a substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”) having a first surface (e.g., top surface of first board part 314) and a second surface (e.g., bottom surface of first board part 314) opposite to the first surface (e.g., top surface of first board part 314), wherein the substrate (e.g., substrate 300) includes a patterned circuit layer (e.g., first trace 320) and defines a through hole (e.g., central slot 313), the patterned circuit layer (e.g., first trace 320) is disposed adjacent to the second surface (e.g., bottom surface of first board part 314) of the substrate (e.g., substrate 300), and an extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) extends to a position corresponding to the through hole (e.g., central slot 313);
disposing an electronic component (e.g., chip 10) over the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300), wherein the electronic component (e.g., chip 10) comprises at least one bump (e.g., bonding pad 12) disposed on and protruded from an active surface (e.g., active surface 11) of the electronic component (e.g., chip 10);
adhering the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) to the first surface of the substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320…”) through an adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”);
an end (e.g., end of first trace 320) of the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) contacting the electronic component (e.g., chip 10) through the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”);
Hung (see, e.g., fig. 4), however, fails to teach the extending portion of the patterned circuit layer is not in direct contact with the active surface of the electronic component and pressing an end of the extending portion of the patterned circuit layer to contact the at least one bump of the electronic component and wherein a periphery of the electronic component is aligned with a periphery of the adhesion layer, such that a lateral surface of the electronic component is aligned with a lateral surface of the adhesion layer, wherein the at least one bump is protruded from the active surface toward the through hole of the substrate.
Chen (see, e.g., figs. 2G-1 – 2G-2), in a similar device to Hung, teaches an at least one bump (e.g., connecting pad 52) disposed on and protruded from an active surface (e.g., active surface 42) thereof toward a through hole (e.g., opening between substrate 10) of a substrate (e.g., substrate 10), and an extending portion (e.g., wire 50) is not in direct contact (see, e.g., connecting pad 52 physically separating the active surface from the wire) with the active surface (e.g., active surface 42) of an electronic component (e.g., chip 40).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the pad protrusion configuration (extending out of the electronic component and protruding toward the through hole, as opposed to protruding inward) of Chen within the setup of Hung, in order to achieve the expected result of increasing the potential space within the electronic component for other components as necessary, while simultaneously reducing the wire length required to enable the connectivity requirements within the device. Note that configuring the pad in this manner would leave it directly surrounded by the elastomer/adhesion layers.
Hung in view of Chen, however, fails to teach pressing an end of the extending portion of the patterned circuit layer to contact the at least one bump of the electronic component, and wherein a periphery of the electronic component is aligned with a periphery of the adhesion layer, such that a lateral surface of the electronic component is aligned with a lateral surface of the adhesion layer.
Kim (see, e.g., fig. 1E), in a similar device to Hung in view of Chen, teaches wherein an adhesion layer (e.g., adhesive 22) is extended from the first portion of an active surface (e.g., surface of chip 21 connected to bonding wires 23) to a periphery of an electronic component (e.g., chip 21) such that a lateral surface of the electronic component (e.g., chip 21) is aligned (e.g., note adhesive 22 and chip 21 are laterally aligned, see fig. 1E) with a lateral surface of the adhesion layer (e.g., adhesive 22).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the lateral alignment configuration of Kim within the chip and adhesion layer configuration of Hung in view of Chen, in order to achieve the expected result of reducing the cost of material of the adhesion layer while manufacturing the device, while simultaneously providing a full adhesive interface between the chip and the substrate.
Hung in view of Chen further in view of Kim, however, fails to teach pressing an end of the extending portion of the patterned circuit layer to contact the at least one bump of the electronic component.
Kang (see, e.g., fig. 6), in a similar device to Hung in view of Chen further in view of Kim, teaches pressing (see, e.g., paragraph 52 “When the bonding wire 91 is bonded to the bonding pad 40 of the upper semiconductor chip 100B using a capillary (not shown), the capillary may press against the bonding pad 40 of the upper semiconductor chip 1006”) an end of a wire bond (e.g., bonding wire 91) to contact a bump (e.g., bonding pad 40) of an electronic component (e.g., upper semiconductor chip 100B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pressing methodology of Kang to contact the patterned circuit layer and the bump of the electronic component of Hung in view of Chen further in view of Kim, as pressing was a well-known technique in the art at the time of filing the invention for contacting a conductive member and a pad/bump, as taught by Kang.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view Chen further in view Kim, Kang, Li and Bowers (US 20220115301 A1).
Regarding claim 12, Hung in view of Chen further in view of Kim and Kang fails to show providing a metal foil on a second surface of the substrate, patterning the metal foil to form a patterned circuit layer, while it also fails to show removing a portion of the substrate from a first surface of the substrate to form a through hole and expose the extending portion of the patterned circuit layer.
Li (see, e.g., fig. 1), in a similar device to Hung in view of Chen further in view of Kim and Kang, teaches providing a metal foil (e.g., metal foil 108) on a surface of the substrate (e.g., integrated circuit die 102), while it also teaches patterning a metal foil to form a patterned circuit layer (see, e.g., paragraph 20 “The metal foil 108 is etched in a pattern to create metal traces…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal foil on the substrate and form the patterned circuit layer of Hung in view of Chen further in view of Kim and Kang from the metal foil of Li, to achieve the expected result of providing conductive properties within the layer in order to give the substrate an electrical connector, allowing the transfer of current as necessary between the electronic component and the substrate/external terminals.
Hung in view of Chen further in view of Kim, Kang, and Li, however, fails to teach removing a portion of the substrate from a first surface of the substrate to form a through hole and expose the extending portion of the patterned circuit layer.
Bowers (see, e.g., figs 11C to 11D), in a similar device to Hung in view of Chen further in view of Kim, Kang, and Li, teaches removing (see, e.g., paragraphs “cavities 611 can be formed at side 610A of substrate 610. In some examples, cavities 611 can be formed by partial-etching side 610A of substrate 610. Portions of cavities 611, vertically aligned with openings 110E, can expose substrate encapsulant 615 formed in openings 110E. In some examples, substrate encapsulant 615 can be coplanar with cavity base 6111…”) a portion of a substrate (e.g., substrate 610) from a surface (e.g., side 610A) of the substrate (e.g., substrate 610).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the substrate exposure of Bowsers (see, e.g., fig. 1) onto the substrate of Hung in view of Chen further in view of Kim, Kang and Li, in order to allow an exposed region of the electronic component to make contact with the substrate’s metal foil through the package encapsulant.
Regarding claim 13, Hung (see, e.g., fig. 4) shows a length of the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) is greater than a thickness (e.g., note that the first trace 320 extends from below the bottom surface of first board 314 above the top surface of first board 314, so the length of the first trace 320 is greater than the first board 314’s thickness) of the substrate (e.g., substrate 300).
Chen (see, e.g., fig. 2G-2) teaches wherein a thickness of the adhesion layer (e.g., adhesive element 30) is greater than a height of the at least one bump (e.g., connecting pad 52), such that the at least one bump (e.g., connecting pad 52) is surrounded by the adhesion layer (e.g., adhesive element 30) toward the through hole of the substrate (e.g., substrate 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness configuration of Chen within the device of Hung in view of Chen further in view of Kim, Kang, Li, and Bowers, in order to achieve the expected result of reducing the size of thickness of the bump, thus reducing the cost of material manufacturing within the device, as well as increasing the extension depth of the wires within the through hole configuration, providing additional room within the through hole area, as opposed to large-thickness bumps protruding substantially out of the through hole region (also note the depth of the through hole region is substantially affected by the thickness of the adhesion layer). In addition, also note that the bump of Hung within fig. 4 is drawn to be substantially smaller in thickness than the adhesion layer, and it would have been obvious to one of ordinary skill in the art at the time of filing the invention to optimize the size of the pads for space within the through hole region as necessary.
Regarding claim 14, Hung (see, e.g., fig. 4) shows wherein pressing the end (e.g., end of first trace 320) of the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) includes pressing the end (e.g., end of first trace 320) of the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) to move through the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300) and the adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”).
Regarding claim 15, Hung (see, e.g., fig. 4) shows forming a package body (e.g., encapsulant 40) to encapsulate the extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320) and the electronic component (e.g., chip 10).
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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