Prosecution Insights
Last updated: April 19, 2026
Application No. 18/223,528

ELECTRONIC DEVICE

Non-Final OA §102§103§112
Filed
Jul 18, 2023
Examiner
GUMEDZOE, PENIEL M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
87%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
1080 granted / 1302 resolved
+14.9% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
1325
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
40.7%
+0.7% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1302 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 07/18/23 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 7 recites “the component comprises an antenna disposed between the first electronic component and the antenna” (emphasis added). It is unclear how the antenna disposed between the first electronic component and itself. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 9 and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2014/0185264). a. Re claim 1, Chen et al. disclose an electronic device, comprising: a first electronic component 307 (see fig. 2d and related text; see [0029] and remaining of disclosure for more details); a plurality of second electronic components 305 disposed under the first electronic component; and a plurality of conductive elements 207 (labeled and unlabeled) electrically connecting (via at least the unlabeled vertical through-via 207 between component 305) the first electronic component to the plurality of second electronic components, wherein the plurality of conductive elements are free from vertically overlapping the plurality of second electronic components (explicit on fig. 2d). b. Re claim 2, the electronic device of claim 1, further comprises: an encapsulant (upper and lower encapsulants 113; [0017]) encapsulating a lateral surface of the first electronic component. c. Re claim 3, the encapsulant encapsulates (via the lower 113) the plurality of second electronic components and the plurality of conductive elements. d. Re claim 4, at least one of the plurality of second electronic components has a passive (top) surface facing the first electronic component and an active (bottom) surface opposite to the passive surface, and the encapsulant covers the active surface (explicit on fig. 2d). e. Re claim 9, the electronic device of claim 1, further comprises: a redistribution structure (lower 101&203&215&209; see [0017]) disposed under the plurality of second electronic components, wherein the plurality of conductive elements are electrically connected to the plurality of second electronic components by the redistribution structure (explicit on fig. 2d). f. Re claim 11, Chen et al. disclose an electronic device, comprising: a first electronic component 307 (see fig. 2d and related text as well as remaining of disclosure for more details); a plurality of second electronic components 305 disposed under the first electronic component; and a first circuit layer (lower 101&203&215&209; see [0017]) disposed under the plurality of second electronic components, wherein the first electronic component is electronically connected (via at least labeled and unlabeled vertical through-via 207, especially the one between chips 305)) to the plurality of second electronic components by the first circuit layer. g. Re claim 12, the plurality of second electronic components do not vertically overlap each other (explicit on fig. 2d). h. Re claim 13, the electronic device of claim 11, further comprises: an encapsulant (upper and lower encapsulants 113) encapsulating (by its lower 113) the plurality of second electronic components; and a conductive element 207 (labeled and unlabeled) penetrating the encapsulant and electrically connecting the first circuit layer and the first electronic component. Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 8,273,604). a. Re claim 18, Kim et al. disclose an electronic device, comprising: a first electronic component 124 (see fig. 10 and related text; see col. 7 ln. 25-31); and a second electronic component 186 (col. 12 ln. 52-57) disposed under the first electronic component (as seen in the orientation of fig. 10 below) and spaced apart from the first electronic component by an adhesive layer 184 (col. 12 ln. 52-57), wherein the electronic device provides an electrical path (see dashed lines on fig. 10 below) passing through the first electronic component and the second electronic component without passing through the adhesive layer. PNG media_image1.png 484 817 media_image1.png Greyscale b. Re claim 19, the electronic device of claim 18, further comprises: a plurality of conductive elements 200 (longer ones; see col. 13 ln. 32-40) disposed under the first electronic component and adjacent to the second electronic component, wherein the electrical path passes through at least one of the plurality of conductive elements (explicit on fig. 10 above); and a conductive layer (204 combined with the shorter elements 200) extending from a lower surface of the second electronic component to a lower surface of the at least one of the plurality of conductive elements. c. Re claim 20, the electronic device of claim 19, further comprises: an encapsulant 194 (col. 13 ln. 1-11) covering the second electronic component and disposed between the conductive layer and the second electronic component, wherein the encapsulant contacts the adhesive layer (explicit on fig. 10). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2014/0185264). a. Re claim 10, Chen et al. disclose all the limitations of claim 1 as stated above except explicitly for the electronic device of claim 1, further comprising a heat dissipating element disposed over the first electronic component. However, it is conventionally known in the art to attach a heat dissipation element such a heat sink to an electronic package in order to enhance heat dissipation. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided a heat sink attached to the top surface of the upper encapsulant 113 in order to enhance heat dissipation (see MPEP 2144.I&II). b. Re claim 14, Chen et al. disclose all the limitations of claim 1 as stated above except explicitly that an upper surface of the encapsulant is substantially aligned with a passive surface of the first electronic component. However, it is conventionally known in the art to provide encapsulated chips of a chip package with surfaces exposed from the said encapsulant and coplanar with a surface of the said encapsulant in order to either enhance heat dissipation from said exposed surfaces, or to allow attachment of a heat sink to said exposed surfaces in order to enhance heat dissipation. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided an upper surface of the encapsulant to substantially aligned with a passive (top) surface of the first electronic component (and also component 309), thus exposing said passive surface from upper encapsulant 113, and this in order to enhance heat dissipation from said passive surface, or to allow attachment of a heat sink to said passive surface in order to enhance heat dissipation (see MPEP 2144.I&II). Allowable Subject Matter Claims 5-6, 8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 9,613,942), Yu et al. (US 2019/0074261), Yee et al. (US 2017/0062383) and Kung et al. (US 2023/0065615) disclose structures similar to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jul 18, 2023
Application Filed
Jan 24, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
87%
With Interview (+3.7%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1302 resolved cases by this examiner. Grant probability derived from career allow rate.

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