DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-10, 21 in the reply filed on 11/30/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim(USPGPUB DOCUMENT: 2021/0280540, hereinafter Kim) in view of Choe (USPGPUB DOCUMENT: 2017/0330862, hereinafter Choe).
Re claim 1 Kim discloses in Fig 12 a three-dimensional (3D) integrated circuit structure, comprising: a first semiconductor structure comprising a first plurality of dies(241/243/245) molded by a first gap-fill material(250)[0029], and a first re-distribution layer(240) electrically connected to the first plurality of dies(241/243/245), wherein the first re-distribution layer(240) comprises a plurality of first bonding pads(bonding pads of 244 structure)[0026] and a first insulating layer(242) around the plurality of first bonding pads(bonding pads of 244 structure)[0026] ; and a second semiconductor structure comprising a second plurality of dies(223/1225/1227) molded by a second gap-fill material(230)[0029], wherein the second plurality of dies(223/1225/1227) comprises at least one through-silicon via (TSV) die[0093], and a second re-distribution layer(210) electrically connected to the second plurality of dies(223/1225/1227), wherein the second re-distribution layer(210) comprises a plurality of second bonding pads(bonding pads of 214 structure) and a second insulating layer(212) around the plurality of second bonding pads(bonding pads of 214 structure),
Kim does not disclose wherein the plurality of first bonding pads(bonding pads of 244 structure)[0026] is directly bonded to the plurality of second bonding pads(bonding pads of 214 structure), respectively.
Choe discloses in Fig 2 wherein the plurality of first bonding pads(236) is directly bonded (by way of 234) to the plurality of second bonding pads(237), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Choe to the teachings of Kim in order to have high bandwidth and high capacity devices [0004, Choe].
Re claim 2 Kim and Choe disclose the 3D integrated circuit structure according to claim 1, wherein the plurality of first bonding pads(bonding pads of 244 structure)[0026] and the plurality of second bonding pads(bonding pads of 214 structure) comprise copper pads.
Re claim 3 Kim and Choe disclose the 3D integrated circuit structure according to claim 1, wherein the first insulating layer(242) and the second insulating layer(212) comprise silicon oxide[0029], silicon nitride, or silicon carbonitride.
Re claim 4 Kim and Choe disclose the 3D integrated circuit structure according to claim 1, wherein the first insulating layer(242) is directly bonded to the second insulating layer(212).
Re claim 5 Kim and Choe disclose the 3D integrated circuit structure according to claim 1 further comprising: a third re-distribution layer(220) disposed on a side of the second semiconductor structure opposite to the second re-distribution layer(210).
Re claim 6 Kim and Choe disclose the 3D integrated circuit structure according to claim 5 further comprising: a plurality of connecting elements(1207/1205) disposed on the third re-distribution layer(220).
Re claim 7 Kim and Choe disclose the 3D integrated circuit structure according to claim 6, wherein the plurality of connecting elements(1207/1205) comprises solder bumps or solder balls.
Re claim 8 Kim and Choe disclose the 3D integrated circuit structure according to claim 5, wherein the TSV die[0093] comprises a plurality of through-silicon vias for electrically connecting the second re-distribution layer(210) with the third re-distribution layer(220).
Re claim 9 Kim and Choe disclose the 3D integrated circuit structure according to claim 5 further comprising: a plurality of conductive posts(conductive posts of 244 structure)[0026] embedded in the first gap-fill material(250)[0029] for electrically connecting to the second re-distribution layer(210).
Re claim 10 Kim and Choe disclose the 3D integrated circuit structure according to claim 1, wherein the first gap-fill material(250)[0029] and the second gap-fill material(230)[0029] comprise dielectric material or molding compound.
Re claim 21 Kim discloses in Fig 12 a three-dimensional (3D) integrated circuit structure, comprising: a first semiconductor structure comprising a first plurality of dies(241/243/245) and a plurality of conductive posts(conductive posts of 244 structure)[0026] molded by a first gap-fill material(250)[0029], and a first re-distribution layer(240) electrically connected to the first plurality of dies(241/243/245) and the plurality of conductive posts, wherein the first re-distribution layer(240) comprises a plurality of first bonding pads(bonding pads of 244 structure)[0026] and a first insulating layer(242) around the plurality of first bonding pads(bonding pads of 244 structure)[0026] ; and a second semiconductor structure comprising a second plurality of dies(223/1225/1227) molded by a second gap-fill material(230)[0029], a second re-distribution layer(210) electrically connected to the second plurality of dies(223/1225/1227), and a third re-distribution layer(220) disposed on a side of the second semiconductor structure opposite to the second re-distribution layer(210); wherein the second re-distribution layer(210) comprises a plurality of second bonding pads(bonding pads of 214 structure) and a second insulating layer(212) around the plurality of second bonding pads(bonding pads of 214 structure),
Kim does not disclose wherein the plurality of first bonding pads(bonding pads of 244 structure)[0026] is directly bonded to the plurality of second bonding pads(bonding pads of 214 structure), respectively.
Choe discloses in Fig 2 wherein the plurality of first bonding pads(236) is directly bonded(by way of 234) to the plurality of second bonding pads(237), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Choe to the teachings of Kim in order to have high bandwidth and high capacity devices [0004, Choe].
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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