DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SASAKI (US 20150060970 A1, hereinafter Sasaki)
With regards to claim 11, Sasaki discloses a memory cell structure (FIGS. 1A-1F) comprising:
a semiconductor substrate (semiconductor substrate 2) with an semiconductor surface;
an active region (active region below region 12) in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region; (region containing and between insulation region I)
a transistor formed based on the active region, (See FIG. 1b) the transistor comprising a gate structure, (word line WL) a first conductive region, (left impurity region 12) and a second conductive region; (ight impurity region 12) and
a capacitor (capacitor C) with a signal electrode (at least lower electrode 86 and at least layer 53 of storage contact SC) and a counter electrode, (at least electrodes 88 and 89) the capacitor being over the transistor, and the signal electrode electrically being coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor; (See FIG. 1b)
wherein the signal electrode comprises two upward extending pillars, and each upward extending pillar stacks over the active region and laterally expands to make a width of the each upward extending pillar along a direction perpendicular to an extension direction from the second conductive region to the first conductive region is larger than a width along the direction perpendicular to the extension direction from the second conductive region to the first conductive region. (see annotated FIG. 1b, showing the two complete pillars comprising at least electrodes 86 (outermost sidewalls) extending “laterally” “along a width” (up and down the Figure) larger than the active region along a direction perpendicular to an extension region (left to right of the figure) from one impurity region 12 to another impurity region 12 (see also response to arguments)
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With regards to claim 12, Sasaki discloses the memory cell structure of claim 11, wherein the gate structure comprises a gate conductive region (word line WL) and a cap dielectric region (SiN film 18) above the gate conductive region, and a top surface of the gate conductive region is lower than the semiconductor surface. (See FIG. 1b)
With regards to claim 13, Sasaki discloses the memory cell structure of claim 11, wherein the counter electrode comprises a plurality of sub-electrodes electrically connected with each other, each sub-electrode comprises a TiN layer and a boron doped polysilicon layer, (Paragraph [0090]: “the upper electrode 88 (third conductive layer) being a titanium nitride film, and the upper electrode 89 being a polysilicon film doped with boron…”) and the signal electrode comprises Si. (Paragraph [0079]: “A structure of each of the storage-node contact plugs SC …including a lower-layer contact plug formed of the polysilicon film 53…”)
With regards to claim 14, Sasaki discloses the memory cell structure of claim 11, wherein the signal electrode has an H-shape structure covering a top surface and two sidewalls of the gate structure. (see FIG. 1b, showing an “H” shape, where examiner notes that the term “H” shape is incredibly broad)
With regards to claim 15, Sasaki discloses the memory cell structure of claim 14, further comprising:
a bit line (bit line BL) disposed under the semiconductor surface; (see FIG. 1b, showing the disposition under the surface relative to the +Z direction) and
a connecting plug (bit contact BC) electrically connecting the bit line to the first conductive region of the transistor. (See FIG. 1b)
With regards to claim 16, Sasaki discloses the memory cell structure of claim 15, wherein the bit line is disposed within the STI region, and the STI region comprises a set of asymmetric material spacers. (See FIG. 1b, showing the disposition and the assymetrical spacers I)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SASAKI (US 20150060970 A1, hereinafter Sasaki) in view of Moon (US 20050098808 A1).
With regards to claim 17, Sasaki discloses a memory cell structure (FIGS. 1A-1F) comprising:
a semiconductor substrate (semiconductor substrate 2) with an original semiconductor surface;
an active region (active region below region 12) in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region; (region around and between insulation region I)
a transistor formed based on the active region, (See FIG. 1b) the transistor comprising a gate structure, (word line WL) a first conductive region, (left impurity region 12) and a second conductive region; (left impurity region 12) and
a capacitor (capacitor C) with a signal electrode (at least lower electrode 86 and at least layer 53 of storage contact SC) and a counter electrode, (at least electrodes 88 and 89) the capacitor being over the transistor, and the signal electrode electrically being coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor; (See FIG. 1b)
wherein the signal electrode comprises two upward extending pillars with rough surface, and each upward extending pillar comprises n+ Poly Si (Paragraph [0074]: “A polysilicon film 53 doped with N-impurities…”.
However, Sasaki does not explicitly teach using Hemispherical-shaped Si in the capacitor structure.
Moon teaches using Hemispherical-grained Si as an alternative to poly-silicon (Paragraph [0011]: “A first aspect of the present invention increases the effective capacitor area by providing a ferroelectric capacitor structure formed on a textured layer. The textured layer causes a subsequently deposited first electrode of the ferroelectric capacitor to have a rugged surface. Preferably, the textured layer comprises textured poly-silicon such as hemispherical grain (HSG) poly-silicon or rugged poly-silicon.”) where the hemispherical grained Si would be hemispherical shaped. (see also response to arguments)
It would have been obvious to one of ordinary skill in the art to modify the device of Sasaki to have the hemispherical Si of Moon, as both references are in the same field of endeavor.
One of ordinary skill would appreciate that using hemispherical Si is substituting one known element for another to obtain predictable results.
With regards to claim 18, Sasaki in view of Moon teaches the memory cell structure of claim 17.
Sasaki further teaches wherein the counter electrode comprises a plurality of sub-electrodes (at least electrodes 88 and 89/90) electrically connected with each other, and a dielectric layer is inserted between every two adjacent sub-electrodes. (see FIG. 1b, showing the dielectrics 82, 87, 91, and 92 between at least every two electrodes)
With regards to claim 19, Sasaki in view of Moon teaches the memory cell structure of claim 18.
Sasaki further teaches wherein each sub-electrode comprises a TiN layer and a boron doped polysilicon layer. (Paragraph [0090]: “the upper electrode 88 (third conductive layer) being a titanium nitride film, and the upper electrode 89 being a polysilicon film doped with boron…”)
With regards to claim 20, Sasaki in view of Moon teaches the memory cell structure of claim 17.
Sasaki further teaches further comprising:
a bit line (bit line BL) disposed under the original semiconductor surface; (see FIG. 1b, showing the disposition under the surface relative to the +Z direction) and
a connecting plug (bit contact BC) electrically connecting the bit line to the first conductive region of the transistor; (See FIG. 1b)
wherein the bit line is disposed within the STI region, and the STI region comprises a set of asymmetric material spacers. (See FIG. 1b, showing the disposition and the assymetrical spacers I)
Response to Arguments
Applicant's arguments filed 05/25/2026 have been fully considered but they are not persuasive.
With regards to claim 11, examiner notes that the amendment does not overcome the current rejection. While Applicant’s arguments try to clarify the direction of extensions, the current amendment is still too broad, and the directions can be interpreted the same as previously presented. In other words, the pillar still has a width in a direction perpendicular to the extension direction (left and right of the page) greater than a width of the active region as described above.
With regards to claim 17, Examiner notes that Moon is being used to suggest that Hemispherical-grained Si is a suitable alternative material to poly-silicon, where Sasaki already teaches poly-silicon in the pillars. Since the hemispherical grained Si is hemispherical shaped, the combination of Sasaki in view of moon would still teach hemispherical shaped Si
Therefore, claims 11 and 17 are properly rejected, and claims 12-16 and 18-20 are rejected for at least their dependencies.
Allowable Subject Matter
Claims 1-10 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nam et al. (US 20060186452 A1) – multi-electrode capacitor with TiN and boron doped polysilicon.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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