Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 11/24/2025 is acknowledged.
Claims 13-14 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/25/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 12, 15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Sheu et. Al. (US 20100289057 A1 hereinafter Sheu).
Regarding claim 1and 20, Sheu teaches in Figs. 1 and 2A with associated text a structure for an electrostatic discharge protection device 200a and method of forming thereof ([0027]), the structure comprising: a semiconductor substrate including a first well (220a and 215a) (Fig. 2A, [0025]); a field-effect transistor 210a including a gate (structures over the channel regions near the source 213a [0017] and [0024]), a source 213a, and a drain 211 (Fig. 2A, [0024]), the source including a first doped region in the first well (Fig. 2A, [0024]-[0025]); and a silicon-controlled rectifier (225a, 220a,230a and 235a) including a first doped region 225a in the first well (Fig. 2A, [0027]).
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Regarding claim 2, Sheu teaches the semiconductor substrate includes a second well 230a adjacent to the first well (Fig. 2A, [0027]), and the silicon-controlled rectifier includes a second doped region 235a in the second well (Fig. 2A, [0027]).
Regarding claim 3, Sheu teaches the semiconductor substrate includes a third well 217 adjacent to the first well (Fig. 2A, [0023]), the drain of the field-effect transistor includes a second doped region 211 in the third well (Fig. 2A), and further comprising: an input-output terminal VDD coupled to the second doped region of the silicon-controlled rectifier and to the second doped region of the field-effect transistor (Fig. 2A, [0024] and [0026]).
Regarding claim 4, Sheu teaches a first shallow trench isolation region 205b in the semiconductor substrate, the first shallow trench isolation region between the first doped region 225a of the silicon-controlled rectifier and the second doped region 235a of the silicon-controlled rectifier (Fig. 2A, [0023] and [0026]), the first shallow trench isolation region including a first portion that overlaps with the first well, and the first shallow trench isolation region including a second portion that overlaps with the second well (Fig. 2A).
Regarding claim 5, Sheu teaches a second shallow trench isolation region 205a in the semiconductor substrate, wherein the second doped region of the silicon-controlled rectifier is disposed between the first shallow trench isolation region and the second shallow trench isolation region (Fig. 2A).
Regarding claim 6, Sheu teaches the semiconductor substrate has a top surface )upper surface including 225a250b, 235a, 205a, etc.), and the first shallow trench isolation region, the second shallow trench isolation region, and the second doped region of the silicon-controlled rectifier are disposed fully between the second well and the top surface of the semiconductor substrate (Fig. 2A).
Regarding claim 7, Sheu teaches the semiconductor substrate includes a third well 217 (Fig. 2A, [0023]), the first well is disposed in a lateral direction between the second well and the third well (Fig. 2A), the drain of the field-effect transistor includes a second doped region 211 in the third well, and the third well includes a portion beneath the gate of the field-effect transistor (see annotated Fig. above).
Regarding claim 8, Sheu teaches the semiconductor substrate includes a deep well 240 having an opposite conductivity type (p-type [0028]) from the second well and the third well (n-type [0023] and [0025]), and the second well and the third well are disposed within the deep well (240 is a guard ring surrounding the structure so that 230a and 17 are within it Fig. 2A, [0028]) also see 340 in Fig. 3 [0031]) .
Regarding claim 9, Sheu teaches the second doped region of the field-effect transistor has a conductivity type (211 is doped using the same process as 225a [0036] and so are n+ type [0026]), and the third well has the conductivity type (n type [0023]) at a lower dopant concentration than the second doped region of the field-effect transistor (217 is n type and so has lower concentration than 211 which has n+ type).
Regarding claim 12, Sheu teaches the first doped region of the source of the field- effect transistor and the first doped region of the silicon-controlled rectifier are coupled to a ground potential (Fig 2A, [0024] and [0026]).
Regarding claim 15, Sheu teaches a shallow trench isolation region 205D in the semiconductor substrate between the gate of the field-effect transistor and the drain of the field-effect transistor (see annotated Fig. above).
Regarding claim 17, Sheu teaches the silicon-controlled rectifier is adjacent to the source of the field-effect transistor (Fig. 2A).
Regarding claim 18, Sheu teaches a shallow trench isolation region 205c in the semiconductor substrate between the first doped region of the source of the field-effect transistor and the first doped region of the silicon-controlled rectifier (Fig. 2A, [0023]).
Regarding claim 19, Sheu teaches the semiconductor substrate has a top surface, the first doped region of the source of the field-effect transistor adjoins the top surface, and the first doped region of the silicon-controlled-rectifier adjoins the top surface (Fig. 2A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Sheu as applied to claim 1 and further in view of Qiao (US 20210273095 A1 hereinafter Qiao).
Regarding claim 10, Sheu teaches the structure of claim 1 wherein the first doped region of the silicon-controlled rectifier has a first conductivity type (n-type [0026]), the first well has a second conductivity type (p type [0025]) opposite from the first conductivity type.
Sheu does not specify the first doped region of the field-effect transistor has the first conductivity type.
Qiao discloses in Figs. 6 with associated text a field-effect transistor LDMOS similar to that of Sheu wherein a source comprising a first doped region 111 of the field-effect transistor has the first conductivity type [0033[
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the first doped region of the field-effect transistor of Sheu have the first conductivity type because according to Qiao the structure is suitable to use a source (111 is connected to the source electrode 152 [0033]) in a DMOS device particularly an LDMOS [0036] furthermore it is very well known in the art to make the source the opposite conductivity type to the body region in a DMPS structure.
Regarding claim 11, Sheu teaches the first conductivity type is n-type, and the second conductivity type is p-type ([0025] and [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897