DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group I in the reply filed on December 19 2025 is acknowledged. Applicant has cancelled claims 11-16 which were drawn to invention Group II.
Claims 1-10 are examined. The Restriction/Election Requirement is made final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “forming a stacked structure of layers over the insulating encapsulation, wherein layers in the stacked structure include electrically insulating material and respective patterns of electrically conductive material…”. It is unclear what “respective patterns” is intended to require for the patterns of electrically conductive material as “respective” typically means separate, or particular (see Merriam-Webster online dictionary definition for respective, adj.). Based on the claim language, it is unclear what Applicant has intended to require of the patterns of electrically conductive material as they relate to the electrically insulating material. Similarly, claims 6-8 use the label “respective” for “patterns of locations”, it is also unclear as to the labeling of these elements as “respective”.
Claim 3 requires the limitation “as well as at least one pattern of electrically conductive material having said geometric distribution”. It is unclear as to whether the “at least one pattern of electrically conductive material” is meant to be the same electrically conductive material as the “respective patterns of electrically conductive material” with the geometrical distribution of claim 1.
Similarly, claims 4 and 5 recite “respective patterns of electrically conductive material” and depend on claim 3, thus it is unclear which electrically conductive material is being referred to throughout the claims in which the element is recited.
The Examiner understands the above issues as potentially erroneous on part of a translation, and suggests amending the claims to be consistent with the labeling of each element throughout the claims.
Claims 9 and 10 contain the trademark/trade name “Ajinomoto Build-Up Film”. Where a trademark or trade name is used in a claim as a limitation to identify or describe a particular material or product, the claim does not comply with the requirements of 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. See Ex parte Simpson, 218 USPQ 1020 (Bd. App. 1982). The claim scope is uncertain since the trademark or trade name cannot be used properly to identify any particular material or product. A trademark or trade name is used to identify a source of goods, and not the goods themselves. Thus, a trademark or trade name does not identify or describe the goods associated with the trademark or trade name. In the present case, the trademark/trade name is used to identify/describe layers of the stacked structure and, accordingly, the identification/description is indefinite.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang et al. (“Tang” US 2022/0028593).
Regarding claim 1, Tang discloses a method (Figures 1-22), comprising:
embedding at least one semiconductor chip (102/106) in a first portion of an insulating encapsulation (120, lateral edges of encapsulation 120, see Figures 1 and 21); and
forming at least one electrically conductive coil (109/111) over a second portion of the insulating encapsulation (120, central portion of encapsulation 120) embedding the at least one semiconductor chip (102/106), said second portion (central portion) at least partly non-overlapping with the first portion (lateral portions, see Figure 22 which shows lateral portions of encapsulation 120 wherein the chips 102/106 are embedded only partially overlaps the region of the encapsulation 120 where the coils 109/11 are on) of the insulating encapsulation (120), wherein the at least one electrically conductive coil (109/111) has a planar coil geometry (see Figures 1 and 22) and a geometrical distribution of electrically conductive connections (110/113/116) to the at least one semiconductor chip (102/106, Figures 1, 1B, 8, and 22 show the electrical connections 110/113/116 of the coils 109/111 connected to the chips 102/106, see also para. [0021]);
wherein forming comprises: forming a stacked structure of layers (107) over the insulating encapsulation (120), wherein layers in the stacked structure include electrically insulating material (501/901/1301) and respective patterns of electrically conductive material (109/111, 110/113/116, see Figure 22);
wherein said respective patterns of electrically conductive material (109/111, 110/113/116) have:
said planar coil geometry (see Figures 1 and 1B) to provide said at least one electrically conductive coil (109/111);
and said geometrical distribution (110/113/116) to provide said electrically conductive connections (110/113/116, see para. [0021] and Figures 1, 1B, and 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tang as applied to claim 1 above, and further in view of Heo et al. (“Heo” US 2022/0399311).
Regarding claim 2, Tang discloses molding an encapsulation material (120) onto the plurality of individual semiconductor chips (102/106, see Figure 21) to embed said plurality of individual semiconductor chips (102/106) in said insulating encapsulation (120, see Figure 21).
Tang does not disclose singulating a semiconductor wafer comprising a plurality of semiconductor chips into a plurality of individual semiconductor chips which include the at least one semiconductor chip and arranging the plurality of individual semiconductor chips on a temporary carrier.
However, Heo discloses in para. [0002]-[0004] singulating a semiconductor wafer (semiconductor substrate/wafer, para. [0003]) comprising a plurality of semiconductor chips (para. [0003]) into a plurality of individual semiconductor chips which include the at least one semiconductor chip and arranging the plurality of individual semiconductor chips on a temporary carrier (support substrate, para. [0004]).
It would have been obvious to one having ordinary skill in the art to incorporate the singulation process of Heo into the teachings of Tang for the purpose of improving productivity in the electronic industry (Heo, para. [0004]).
Regarding claim 3, Tang discloses wherein forming the stacked structure of layers (107) comprises forming a base layer (107) on a surface of the at least one semiconductor chip (102/106), said base layer (107) including electrically insulating material (501/901, see Figure 18) as well as at least one pattern of electrically conductive material (110/113) having said geometrical distribution (110/113 have the geometrical distribution of the coil, connected to the chips 102/106).
Regarding claim 4, Tang further discloses growing said respective patterns of electrically conductive material (109/111, 110/113/116) on said electrically insulating material (501/901, electroplating deposition/growing processes 300, 400, 700, 800, 1100, para. [0029]-[0036]).
Regarding claim 5, Tang discloses wherein growing said respective patterns of electrically conductive material (109/111, 110/113/116, growing processes 300, 400, 700, 800, 1100) on said electrically insulating material (501/901) comprises plating (electroplating process, para. [0029]-[0036]).
Regarding claim 6, Tang discloses wherein forming the stacked structure of layers (107) comprises:
forming in the electrically insulating material (501/901) of the base layer (107) a respective pattern of locations promoting growth of electrically conductive material (109/111, 110/113/116, forming patterns of locations promoting growth of the electrically conductive material is accomplished by masks 301, 401, 701, 801, and 1101 during the electroplating processes, see para. [0029]-[0036]), and
growing electrically conductive material (109/111, 110/113/116) at said locations promoting growth of electrically conductive material (see processes 300, 400, 700, 800 and 1100, which show the electrically conductive material is grown, or electroplated, in locations determined by the patterning masks 301, 401, 701, 801, and 1101).
Regarding claim 8, Tang discloses wherein forming said respective pattern of locations comprises depositing copper or titanium (electroplating processes 300, 400, 700, 800, and 1100 comprise deposition of copper, see para. [0029]-[0036]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tang and Heo as applied to claim 6 above, and further in view of Chew (US 2022/0102254).
Regarding claim 7, Tang does not disclose wherein forming said respective pattern of locations comprises sputtering electrically conductive material at said locations.
However, Chew discloses forming patterns (traces, 142) using a sputtering technique (see para. [0161]) of electrically conductive material (copper, gold, silver, tin, aluminum, etc., para. [0161]) at locations patterned by a film/mask (162).
It would have been obvious to one having ordinary skill in the art to incorporate the sputtering process as taught by Chew into the teachings of Tang for the purpose of utilizing a metallic deposition process that is well-known and suitable in the art for forming conductive traces (see Chew, para. [0161]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Tang and Heo as applied to claim 3 above, and further in view of Zhang et al. (“Zhang” US 2021/0132309).
Regarding claim 9, Tang does not explicitly disclose wherein the layers in the stacked structure of layers are Ajinomoto Build-Up Film layers.
However, Zhang discloses in Figure 1A a package substrate (102), which comprises stacked layers (see Figure 1A), comprised of a dielectric material of Ajinomoto Build-Up Film (ABF, see para. [0059]).
It would have been obvious to one having ordinary skill in the art to incorporate the use of ABF for the stacked structure layers because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Regarding claim 10, Tang does not explicitly disclose wherein the base layer formed on the surface of the semiconductor chip is an Ajinomoto Build-Up Film layer.
However, Zhang discloses in Figure 1A a package substrate (102), which is a base layer formed on the lower surface of the chip 105 (see Figure 1A), comprised of a dielectric material of Ajinomoto Build-Up Film (ABF, see para. [0059]).
It would have been obvious to one having ordinary skill in the art to incorporate the use of ABF for the stacked structure layers because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899