DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (“Tang” US 2022/0028593) in view of Park et al. (“Park” US 2013/0175701).
Regarding claim 1, Tang discloses a method (Figures 1-22), comprising:
molding an insulating encapsulation (120) onto at least one semiconductor chip (102/106) to embed the at least one semiconductor chip (102/106) in a first portion of the insulating encapsulation (120, lateral edges of encapsulation 120, see Figures 1 and 21); and
forming a stacked structure of layers (107) over the insulating encapsulation (120) embedding the at least one semiconductor chip (102/106, see Figures 1 and 21), wherein layers in the stacked structure (107) include electrically insulating material (501/901/1301) and patterns of electrically conductive material (109/111, 110/113/116, see Figure 22), providing at least one electrically conductive coil (109/111) over a second portion of the insulating encapsulation (120, central portion of encapsulation 120), said second portion (central portion) at least partly non-overlapping with the first portion (lateral portions, see Figure 22 which shows lateral portions of encapsulation 120 wherein the chips 102/106 are embedded only partially overlaps the region of the encapsulation 120 where the coils 109/11 are on) of the insulating encapsulation (120) embedding the at least one semiconductor chip (102/106), wherein the at least one electrically conductive coil (109/111) has a planar coil geometry (see Figures 1 and 22) and a geometrical distribution of electrically conductive connections (110/113/116) to the at least one semiconductor chip (102/106, Figures 1, 1B, 8, and 22 show the electrical connections 110/113/116 of the coils 109/111 connected to the chips 102/106, see also para. [0021]);
wherein said patterns of electrically conductive material (109/111, 110/113/116) have:
said planar coil geometry (see Figures 1 and 1B) to provide said at least one electrically conductive coil (109/111);
and said geometrical distribution (110/113/116) to provide said electrically conductive connections (110/113/116, see para. [0021] and Figures 1, 1B, and 22).
Tang does not disclose that the above steps are performed in the order as listed in the claim.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to embed the semiconductor chips in the insulating encapsulation material before forming the stacked structure of layers on the encapsulation embedding the semiconductor chip since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04. Additionally, it is evidenced by Park (see para. [0063]), which discloses that an interconnect structure (analogous to the claims stacked structure of layers) is formed before or after encapsulation of the semiconductor chip, that it is obvious to alter the order of the steps as disclosed by Tang to the claimed order, since either order may be used to form an interconnect structure and an embedded chip.
Regarding claim 3, Tang discloses wherein the step of forming the stacked structure of layers (107) comprises forming a layer (107), said layer (107) including electrically insulating material (501/901, see Figure 18) as well as at least one pattern of electrically conductive material (110/113) having said geometrical distribution (110/113 have the geometrical distribution of the coil, connected to the chips 102/106).
Claims 2, 4-6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tang and Park as applied to claims 1 and 3 above, and further in view of Heo et al. (“Heo” US 2022/0399311).
Regarding claim 2, Tang discloses wherein the step of molding comprises molding an encapsulation material (120) onto the plurality of individual semiconductor chips (102/106, see Figure 21) to embed said plurality of individual semiconductor chips (102/106) in said insulating encapsulation (120, see Figure 21).
Tang does not disclose singulating a semiconductor wafer comprising a plurality of semiconductor chips into a plurality of individual semiconductor chips which include the at least one semiconductor chip; and arranging the plurality of individual semiconductor chips on a temporary carrier.
However, Heo discloses in para. [0002]-[0004] singulating a semiconductor wafer (semiconductor substrate/wafer, para. [0003]) comprising a plurality of semiconductor chips (para. [0003]) into a plurality of individual semiconductor chips which include the at least one semiconductor chip and arranging the plurality of individual semiconductor chips on a temporary carrier (support substrate, para. [0004]).
It would have been obvious to one having ordinary skill in the art to incorporate the singulation process of Heo into the teachings of Tang for the purpose of improving productivity in the electronic industry (Heo, para. [0004]).
Regarding claim 4, Tang further discloses growing said patterns of electrically conductive material (109/111, 110/113/116) on said electrically insulating material (501/901, electroplating deposition/growing processes 300, 400, 700, 800, 1100, para. [0029]-[0036]).
Regarding claim 5, Tang discloses wherein growing said patterns of electrically conductive material (109/111, 110/113/116, growing processes 300, 400, 700, 800, 1100) on said electrically insulating material (501/901) comprises plating (electroplating process, para. [0029]-[0036]).
Regarding claim 6, Tang discloses wherein the step of forming the stacked structure of layers (107) comprises:
forming in the electrically insulating material (501/901) of the layer (107) a pattern of locations promoting growth of electrically conductive material (109/111, 110/113/116, forming patterns of locations promoting growth of the electrically conductive material is accomplished by masks 301, 401, 701, 801, and 1101 during the electroplating processes, see para. [0029]-[0036]), and
growing electrically conductive material (109/111, 110/113/116) at said locations promoting growth of electrically conductive material (see processes 300, 400, 700, 800 and 1100, which show the electrically conductive material is grown, or electroplated, in locations determined by the patterning masks 301, 401, 701, 801, and 1101).
Regarding claim 8, Tang discloses wherein forming said pattern of locations comprises depositing copper or titanium (electroplating processes 300, 400, 700, 800, and 1100 comprise deposition of copper, see para. [0029]-[0036]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tang, Park, and Heo as applied to claim 6 above, and further in view of Chew (US 2022/0102254).
Regarding claim 7, Tang does not disclose wherein forming said pattern of locations comprises sputtering electrically conductive material at said locations.
However, Chew discloses forming patterns (traces, 142) using a sputtering technique (see para. [0161]) of electrically conductive material (copper, gold, silver, tin, aluminum, etc., para. [0161]) at locations patterned by a film/mask (162).
It would have been obvious to one having ordinary skill in the art to incorporate the sputtering process as taught by Chew into the teachings of Tang for the purpose of utilizing a metallic deposition process that is well-known and suitable in the art for forming conductive traces (see Chew, para. [0161]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tang and Park as applied to claim 3 above, and further in view of Zhang et al. (“Zhang” US 2021/0132309).
Regarding claim 9, Tang does not explicitly disclose wherein the layers in the stacked structure of layers are film layers.
However, Zhang discloses in Figure 1A a package substrate (102), which comprises stacked layers (see Figure 1A), comprised of a dielectric material of film layers (ABF, see para. [0059]).
It would have been obvious to one having ordinary skill in the art to incorporate the use of ABF for the stacked structure layers because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Response to Arguments
Applicant’s amendments, see claims filed April 21 20206, overcome the 112(b) rejections of claims 1 and 3-9 (claim 10 has been cancelled by Applicant). The 112(b) rejections of claims 1 and 3-9 have been withdrawn.
Applicant’s arguments with respect to the prior art rejection of claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights