Prosecution Insights
Last updated: August 17, 2026
Application No. 18/224,050

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §102§103
Filed
Jul 19, 2023
Priority
Jun 20, 2023 — TW 112123091
Examiner
SALAZ, SAMMANTHA KATELYN
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
24 granted / 27 resolved
+20.9% vs TC avg
Strong +18% interview lift
Without
With
+17.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
24 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
51.4%
+11.4% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 27 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 6/2/2026 have been fully considered but they are not persuasive. Regarding Applicants’ argument for claim 7, Applicant argues that Wang fails to disclose that the barrier layer is in the IMD layer and extended to a top surface of the IMD layer. Examiner respectfully disagrees. The barrier layer, metal layer, and IMD layer of Wang are all coplanar in Fig. 6, meaning that the barrier layer extends to a top surface of the IMD layer. It appears the amendment is intended to read as the barrier layer extends above and across the top surface of the ILD layer, which Examiner would agree Wang fails to teach. However, this is not how the claim is written, and the rejection of claim 7 is below. Regarding Applicants’ argument for claim 1, Applicant argues that Wang fails to disclose planarizing the metal layer while a top surface of the remaining metal layer is higher than a top surface of the IMD layer in amended claim 1. Examiner would like to note that Wang is silent on the details of the planarization step, as the details are not included in their specification for brevity (paragraph [0015]). However, Wang does teach planarizing the metal layer 36 (as also admitted by Applicant in their remarks, page 8 line 1). The claim language says planarizing “while” a top surface of the remaining metal layer is higher than a top of the IMD layer, which does not necessarily read as the top surface is higher after the planarization. The amended language is interpreted to mean that the top surface of the remaining metal is higher than the IMD layer during the planarization step. As Wang does not provide details of the planarization, the metal can either be disposed to a top surface above or below the IMD layer, necessitating another reference for clarity, as will be seen in the rejection of claim 1 below with the inclusion of previously relied upon reference Lien et al. (US 2006/0088947 A1). Regarding the objection to the title, Examiner agrees the amended title is descriptive, and the related objection is withdrawn. Status of the Claims Claims 1-17 are pending in the application and are currently being examined. No claims have been amended. Claims 13-17 have been withdrawn per the 12/29/2025 restriction election. No new claims have been added. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0343786 A1, hereafter Wang). Regarding claim 7, in Fig. 6 Wang discloses a semiconductor device, comprising: an inter-metal dielectric (IMD) layer (28, [0014]) on a substrate (12, [0012]); a metal interconnection (30, [0014]) in the IMD layer (28), wherein the metal interconnection (30) comprises: a barrier layer (34, [0015]) in the IMD layer (28) and extended to a top surface of the IMD layer (28) (as the barrier layer (34) and IMD layer (28) are coplanar in Fig. 6, the barrier layer (34) extends to a top surface of the IMD layer (28)); and a metal layer (36, [0015]) on the barrier layer (34); a spin orbit torque (SOT) layer (channel layer, 42, [0017]) on the barrier layer (34) and the metal layer (36); and a magnetic tunneling junction (MTJ) (58, [0019]) on the SOT layer (42). Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lien et al. (US 2006/0088947 A1, hereafter Lien). Regarding claim 1, Wang discloses a method for fabricating a semiconductor device, comprising: forming an inter-metal dielectric (IMD) layer (28, [0014]) on a substrate (12, [0012]); forming a contact hole (where the barrier layer (34, [0015]) and metal layer (36, [0015]) are deposited) in the IMD layer (28); forming a barrier layer (34) and a metal layer (36) in the contact hole; planarizing the metal layer (planarizing is taught by Wang shown in the description of Fig. 2 [0017] and also admitted by applicant in their remarks on page 8, line 1. Wang more specifically teaches planarizing a channel layer in order to make the channel layer even with the top surface of the surrounding layer ([0017]). So one of ordinary skill in the art would know to utilize a planarizing step on the metal layer in order to have an even or planar surface); forming a spin orbit torque (SOT) layer (channel layer, 42, [0017]) on the barrier layer (34) and the metal layer (36); and forming a magnetic tunneling junction (MTJ) (58, [0019]) on the SOT layer (42). Wang fails to teach a top surface of the remaining metal layer is higher than a top surface of the IMD layer. However, Lien teaches in Figs. 2-4 a process in which a barrier layer (40, [0021]) and a metal layer (42, [0021]) are formed above an IMD layer (dielectric, 24/34, [0018] and [0020]) then planarized. In this step, the top surface of the metal layer (42) is higher than the top surface of the IMD layer (24/34). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer and barrier layer of Wang to be formed like that of Lien to have the metal layer and barrier layer to have top surfaces above the IMD layer in order to have a planar surface to build further layers upon, as Lien teaches in [0022]. Regarding claim 6, Wang in view of Lien teaches the method of claim 1. Wang further teaches the barrier layer comprises titanium nitride (TiN) [0015]. Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Lien as applied to claim 1 above, and further in view of Edelstein et al. (US 2017/0148740 A1, hereafter Edelstein). Regarding claim 2, Wang in view of Lien teaches the method of claim 1. However, Wang fails to teach a doping process on the barrier layer and the metal layer. However, in Figs. 4 and 5, Edelstein teaches a method of doping a surface of a tungsten element (along with the rest of the entirety of exposed surfaces, which would include the barrier layer of Wang) with nitrogen [0028]. This doping is done to repair damages in the tungsten caused by etching [0028]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang to include the nitrogen doping of Edelstein in order to repair etch damage. Regarding claim 3, Wang in view of Lien in view of Edelstein teach the method of claim 2. Edelstein further teaches the doping process includes nitrogen [0028]. Regarding claim 4, Wang in view of Lien in view of Edelstein teach the method of claim 3. Edelstein further teaches the doping process forms an interface layer on the metal layer (36 of Wang, [0015]). As the doping process only dopes the surface of the metal layer, and the doped surface is what is interfacing the later levels, the doping creates an interface layer. Regarding claim 5, Wang in view of Lien in view of Edelstein teach the method of claim 4. Edelstein further teaches the interface layer comprises tungsten nitride (WN). Wang taught the metal layer comprised tungsten, much like the tungsten contacts of Edelstein [0023], the surface becomes tungsten nitride in Fig. 5 of Edelstein [0028]. Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 7 above, and further in view of Edelstein. Regarding claim 8, Wang teaches the semiconductor device of claim 7. Wang fails to disclose an interface layer on the metal layer. However, in Figs. 4 and 5, Edelstein teaches a method of doping a surface of a tungsten element with nitrogen [0028]. As the doping process only dopes the surface of the metal layer, and the doped surface is what is interfacing the later levels, the doping creates an interface layer. This doping is done to repair damages in the tungsten caused by etching [0028]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include the nitrogen doping of Edelstein in order to repair etch damage. Regarding claim 9, Wang in view of Edelstein teach the semiconductor device of claim 8. Edelstein further teaches the interface layer comprises tungsten nitride (WN). Wang taught the metal layer comprised tungsten, much like the tungsten contacts of Edelstein [0023], the surface becomes tungsten nitride in Fig. 5 of Edelstein [0028]. Regarding claim 10, Wang in view of Edelstein teach the semiconductor device of claim 8. Wang in view of Edelstein further discloses top surfaces of the interface layer (dopes surface of metal layer 36 of Wang [0015]) and the barrier layer (34 of Wang, [0015]) are coplanar (as the barrier layer and the metal layer are coplanar, the interface layer is coplanar with the barrier layer). Regarding claim 11, Wang in view of Edelstein teach the semiconductor device of claim 7. Wang further discloses the barrier layer comprises titanium nitride (TiN) [0015]. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 7 above, and further in view of Lien et al. (US 2006/0088947 A1, hereafter Lien). Regarding claim 12, Wang teaches the semiconductor device of claim 7. Wang fails to disclose a top surface of the barrier layer is higher than a top surface of the IMD layer. However, Figs. 4-6 of Lien teaches a similar memory device in which the barrier layer (40, [0021]) being disposed on the entirety of the exposed surface, (which would include the IMD layer of Wang). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include a blanket deposited barrier layer in order to form an underlying electrode for subsequent layers, as Lien teaches in [0025]. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMMANTHA K SALAZ/ Examiner, Art Unit 2892 /NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Jul 19, 2023
Application Filed
Mar 10, 2026
Non-Final Rejection mailed — §102, §103
Jun 02, 2026
Response Filed
Jul 29, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+17.6%)
3y 2m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 27 resolved cases by this examiner. Grant probability derived from career allowance rate.

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