DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-17 are pending in the application and are currently being examined. No claims have been amended. Claims 13-17 have been withdrawn per the 12/29/2025 restriction election. No new claims have been added.
Election/Restrictions
Claims 13-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/19/2023 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2021/0343786 A1, hereafter Wang).
Regarding claim 7, in Fig. 6 Wang discloses a semiconductor device, comprising:
an inter-metal dielectric (IMD) layer (28, [0014]) on a substrate (12, [0012]);
a metal interconnection (30, [0014]) in the IMD layer (28), wherein the metal interconnection (30) comprises:
a barrier layer (34, [0015]) in the IMD layer (28) and extended to a surface of the IMD layer (28); and
a metal layer (36, [0015]) on the barrier layer (34);
a spin orbit torque (SOT) layer (channel layer, 42, [0017]) on the barrier layer (34) and the metal layer (36); and a magnetic tunneling junction (MTJ) (58, [0019]) on the SOT layer (42).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Regarding claim 1, Wang discloses a method for fabricating a semiconductor device, comprising:
forming an inter-metal dielectric (IMD) layer (28, [0014]) on a substrate (12, [0012]);
forming a contact hole (where the barrier layer (34, [0015]) and metal layer (36, [0015]) are deposited) in the IMD layer (28);
forming a barrier layer (34) and a metal layer (36) in the contact hole;
planarizing the metal layer (while planarizing the metal layer is not explicitly taught, Wang teaches planarizing a channel layer in order to make the channel layer even with the top surface of the surrounding layer ([0017]). So one of ordinary skill in the art would know to utilize a planarizing step on the metal layer in order to have an even surface between the metal layer, the barrier layer, and the IMD layer);
forming a spin orbit torque (SOT) layer (channel layer, 42, [0017]) on the barrier layer (34) and the metal layer (36); and
forming a magnetic tunneling junction (MTJ) (58, [0019]) on the SOT layer (42).
Regarding claim 6, Wang teaches the method of claim 1. Wang further teaches the barrier layer comprises titanium nitride (TiN) [0015].
Claim(s) 2-5 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claims 1 and 7 above, and further in view of Edelstein et al. (US 2017/0148740 A1, hereafter Edelstein).
Regarding claim 2, Wang teaches the method of claim 1. However, Wang fails to teach a doping process on the barrier layer and the metal layer. However, in Figs. 4 and 5, Edelstein teaches a method of doping a surface of a tungsten element (along with the rest of the entirety of exposed surfaces, which would include the barrier layer of Wang) with nitrogen [0028]. This doping is done to repair damages in the tungsten caused by etching [0028]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wang to include the nitrogen doping of Edelstein in order to repair etch damage.
Regarding claim 3, Wang in view of Edelstein teach the method of claim 2. Edelstein further teaches the doping process includes nitrogen [0028].
Regarding claim 4, Wang in view of Edelstein teach the method of claim 3. Edelstein further teaches the doping process forms an interface layer on the metal layer (36 of Wang, [0015]). As the doping process only dopes the surface of the metal layer, and the doped surface is what is interfacing the later levels, the doping creates an interface layer.
Regarding claim 5, Wang in view of Edelstein teach the method of claim 4. Edelstein further teaches the interface layer comprises tungsten nitride (WN). Wang taught the metal layer comprised tungsten, much like the tungsten contacts of Edelstein [0023], the surface becomes tungsten nitride in Fig. 5 of Edelstein [0028].
Regarding claim 8, Wang teaches the semiconductor device of claim 7. Wang fails to disclose an interface layer on the metal layer. However, in Figs. 4 and 5, Edelstein teaches a method of doping a surface of a tungsten element with nitrogen [0028]. As the doping process only dopes the surface of the metal layer, and the doped surface is what is interfacing the later levels, the doping creates an interface layer. This doping is done to repair damages in the tungsten caused by etching [0028]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include the nitrogen doping of Edelstein in order to repair etch damage.
Regarding claim 9, Wang in view of Edelstein teach the semiconductor device of claim 8. Edelstein further teaches the interface layer comprises tungsten nitride (WN). Wang taught the metal layer comprised tungsten, much like the tungsten contacts of Edelstein [0023], the surface becomes tungsten nitride in Fig. 5 of Edelstein [0028].
Regarding claim 10, Wang in view of Edelstein teach the semiconductor device of claim 8. Wang in view of Edelstein further discloses top surfaces of the interface layer (dopes surface of metal layer 36 of Wang [0015]) and the barrier layer (34 of Wang, [0015]) are coplanar (as the barrier layer and the metal layer are coplanar, the interface layer is coplanar with the barrier layer).
Regarding claim 10, Wang in view of Edelstein teach the semiconductor device of claim 7. Wang further discloses the barrier layer comprises titanium nitride (TiN) [0015].
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 7 above, and further in view of Lien et al. (US 2006/0088947 A1, hereafter Lien).
Regarding claim 12, Wang teaches the semiconductor device of claim 7. Wang fails to disclose a top surface of the barrier layer is higher than a top surface of the IMD layer. However, Figs. 4-6 of Lien teaches a similar memory device in which the barrier layer (40, [0021]) being disposed on the entirety of the exposed surface, (which would include the IMD layer of Wang). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wang to include a blanket deposited barrier layer in order to form an underlying electrode for subsequent layers, as Lien teaches in [0025].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights