Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 21 objected to because of the following informalities: Claims 21 line 7 replace “surface8,” with “surface.” . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 14 recited the limitations “the first interconnect structure”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. (US 2013/0015587, as disclosed in previous office action).
As for claim 1, Okutsu et al. disclose in Figs. 12-13 and the related text a semiconductor package, comprising:
a first integrated circuit die 121A having a first cutting (side) surface, wherein the first integrated circuit die 121A comprises a first edge interconnect feature (left portion 27W) extending to the first cutting surface 21L (FIG. 12/13);
a second integrated circuit die 121B having a second cutting (side) surface, wherein the second integrated circuit die 121B comprises a second edge interconnect feature (right portion of 27W) extending to the second cutting surface 21L (fig. 12/13); and
an inter-chip connector (middle portion of 27W) having a first end contacting the first edge interconnect feature and a second end contacting the second edge interconnect feature (fig. 12/13), wherein the inter-chip connector (middle portion of 27W) is a conductive column disposed at a same level as the first integrated circuit die 121A and the second integrated circuit die 121B (see fig. 13, [0083]),
wherein the first integrated circuit die 121A comprises a circuit region 21IA surrounded by a seal region 21G1 (Fig. 12), the first edge interconnect feature (left portion 27W) is formed in an IMD (inter metal dielectric) layer 25-27 in the first interconnect structure and extend from the circuit region through an opening (where left portion 27W formed in) in the seal region 21G1 to the first cutting surface (fig. 13).
Okutsu et al. do not disclose a diameter of the conductive column varies, and the diameter is larger adjacent the first and second edge interconnect features and smaller away from the first and second edge interconnect features.
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, chip connector, solder ball/bump, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Okutsu et al. to include the diameter of the conductive column as taught by Hollis, in order to improve bonding strength.
As for claim 3, Okutsu et al. disclose the semiconductor package of claim 2, wherein the first interconnect structure comprises: a conductive feature 25Gw embedded in the circuit region 21IA in the IMD layer 25-29, wherein an inner (left) end of the first edge interconnect feature is (electrically) connected to the conductive feature (fig. 13), and an outer (right) end of the first edge interconnect feature extends to the first cutting surface of the first interconnect feature (fig. 12/13).
As for claim 4, Okutsu et al. disclose the semiconductor package of claim 3, wherein the first interconnect structure further comprises a first sealing ring 21IA and a second sealing ring 21IB, the first sealing ring 21IA has a first opening (where left portion 27W formed in), the second sealing ring 21IB has a second opening (where right portion 27W formed in) aligning with the first opening, and the first edge interconnect feature extends through the first opening in the first sealing ring and the second opening in the second sealing ring (Fig. 13).
As for claim 6, Okutsu et al. disclose the semiconductor package of claim 3, wherein the first integrated circuit die 121A further comprises a plurality of external contacts 21B/30T formed on the first interconnect structure (fig. 13).
As for claim 7, Okutsu et al. disclose the semiconductor package of claim 6, further comprising an interposer substrate 20 (electrically) attached to the plurality of external contacts 21B/30T of the first integrated circuit die [0141].
Claim(s) 5 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. in view of Do et al. (US 2008/0272504, as disclosed in previous office action).
As for claims 5 and 21, Okutsu et al. disclose the semiconductor package of claim 1, wherein the first integrated circuit die 121A includes a first substrate 20, the second integrated circuit die 121B includes a second substrate 20, wherein the first and second cutting surfaces are facing each other (Fig. 12), and at least a portion of the inter-chip connector (middle portion of 27W) is disposed between the first cutting surface and the second cutting surface (fig. 12).
Okutsu et al. do not disclose an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, wherein the encapsulant layer is disposed between the first and second substrates.
Do et al. teach in Figs. 9A-9B and the related text an encapsulant layer 602 formed between the first integrated circuit die and the second integrated circuit die, wherein the plurality of inter-chip connectors 206/902 are embedded in the encapsulant layer 602, wherein the encapsulant layer 602 is disposed between the first and second substrates (a portion/another portion 404 below 200).
Okutsu et al. and Do et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, wherein the encapsulant layer is disposed between the first and second substrates as taught by Do et al., in order to provide protection for semiconductor chips.
Claim(s) 8, 9, 11, 13-14 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. (US 2020/0066651, as disclosed in the previous office action) in view of Lu (US 2017/0287871, as disclosed in the previous office action).
As for claim 8-9, Burton et al. disclose in Figs. 3A-3B and the related text a semiconductor package, comprising:
a substrate (mother/print circuit board, [0065])
a first integrated circuit die 308A attached to the substrate, wherein the first integrated circuit die 308A includes a first semiconductor substrate 332 (similar to 100 [0022]), the first integrated circuit die has a first cutting (side) surface, and the first cutting surface extends through the first semiconductor substrate (fig. 3B);
a second integrated circuit die 308B attached to the substrate adjacent the first integrated circuit die (FIG. 3A-3B), wherein the second integrated circuit die 308B has a second cutting (side) surface, the second integrated circuit die 308B includes second semiconductor substrate 332 (similar to 100 [0022]), and the second cutting surface extends through the second semiconductor substrate (Fig. 3B), and the first cutting surface faces the second cutting surface (fig. 3A-3B); and
a plurality of inter-chip connectors 330C/324C formed between the first integrated circuit die and second integrated circuit die (FIG. 3A-3B) and vertically separated from the substrate [0065], wherein a first (left) end of each of the inter-chip connector contacts the first cutting surface and a second (right) end of the inter-chip connector contacts the second cutting surface (fig. 3B).
Okutsu et al. dos not disclose the substrate with through vias formed within the substrate, wherein the substrate is an interposer substrate, and the first integrated circuit die connected to the interposer substrate through a plurality of first external contacts.
Lu teaches in Fig. 1 and the related text a substrate 103 with through vias 106a/106b formed within the substrate, wherein the substrate 103 is an interposer substrate, and the first integrated circuit die 122/121 connected to the interposer substrate through a plurality of first external contacts 123/124.
Burton et al. and Lu are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Burton et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Burton et al. to include the limitations as taught by Lu in order to support the plurality of dies provide interconnection.
As for claim 11, Burton et al. disclose the semiconductor package of claim 8, wherein the first integrated circuit die 121A comprises :
one or more transistors 336B (similar to 222D, [0032]) formed in and on a semiconductor substrate 332 (fig. 3B);
an interconnect structure 344A comprising two or more IMD layers (ILD) formed over the one or more transistors (Fig. 3B); and
a plurality of edge interconnect features 330A/330B or 324A/324B, wherein each of the plurality of edge interconnect feature has an inner end embedded in one of the two or more IMD layers and an outer end in contact with one of the plurality of the inter-chip connectors (fig. 3B).
As for claim 13, Burton et al. disclose the semiconductor package of claim 11, wherein the first integrated circuit die 308A has four cutting surfaces including the first cutting surface (fig. 1, also see Fig. 2A), and the plurality of edge interconnect features are symmetrically distributed along all of the four cutting surfaces of the first integrated circuit die (fig. 1, also see Fig. 2A).
As for claim 14, Burton et al. disclose the semiconductor package of claim 13, further comprises a plurality of conductive bumping features 350A/350B in (electrically) contact with the plurality of edge interconnect features on all of the four cutting surfaces of the first integrated circuit die (fig. 1, 2A and 3A-3B).
As for claim 22, Burton et al. disclose the semiconductor of package of claim 8, wherein the first integrated circuit die 308A comprises:
a first device layer 336B formed on the first semiconductor substrate 332 (fig. 3B);
an first interconnect structure 344A comprising formed over the device layer (fig. 3B), wherein a conductive feature 348A in the interconnect structure is in contact with one of the plurality of the inter-chip connectors 330C/324C and the substrate with through vias formed within is disposed on the first interconnect structure (Burton et al. in view of Lu).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. in view of Lu and further in view of Do et al.
As for claim 10, Burton et al. disclose the semiconductor package of claim 9, further comprising an encapsulant layer, wherein the plurality of inter-chip connectors are embedded in the encapsulant layer.
Do et al. teach in Figs. 9A-9B and the related text an encapsulant layer 602, wherein the plurality of inter-chip connectors 206/902 are embedded in the encapsulant layer 602.
Burton et al. and Do et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Burton et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Burton et al. to include an encapsulant layer, wherein the plurality of inter-chip connectors are embedded in the encapsulant layer as taught by Do et al., in order to provide protection for semiconductor chips.
Claim(s) 12 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. in view of Lu and further in view of Okutsu et al.
As for claims 12 and 23, Burton et al. and Lu disclosed the semiconductor package of claim 11, except the interconnect structure comprises a sealing ring formed in the two or more layers, and the plurality of edge interconnect features extend through openings in the sealing ring and a second sealing ring formed around the first sealing ring, the second sealing includes a plurality of second openings, the plurality of first openings and the plurality of second openings are formed in the same IMD layer, and the plurality of edge interconnect features extend through the plurality of second openings in the second sealing ring.
Okutsu et al. teach in Figs. 12-13 and the related text the interconnect structure comprises a sealing ring 21G2 formed in the two or more IMD layers 25-29, and the (27Bw) plurality of edge interconnect features 27Bw/27W extend through openings in the sealing ring (fig. 13) and a second sealing ring 21G1 formed around the first sealing ring (fig. 12), the second sealing 21G1 includes a plurality of second openings, the plurality of first openings and the plurality of second openings are formed in the same IMD layer (Fig. 13), and (27W of) the plurality of edge interconnect features 27Bw/27W extend through the plurality of second openings in the second sealing ring.
Burton et al., Lu and Okutsu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Okutsu et al. in order to prevent cracking (Okutsu et al. [0007]).
Claim(s) 15, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. (US 2020/0066651, as disclosed in previous office actions) in view of Do et al.
As for claim 15, Burton et al. disclose in Figs. 3A-3B and the related text a semiconductor package, comprising:
a first integrated circuit die 308A comprising:
a first semiconductor substrate 332 ([0022], [0044]);
a first interconnection structure 340A/348A formed on the first semiconductor substrate, the first interconnect structure having a first edge interconnect feature 330A (FIG. 3A-3B); and
a plurality of first external contacts 324A/350A formed over the first interconnect structure;
a second integrated circuit die 308B comprising:
a second semiconductor substrate 332 ([0022] , [0044]);;
a second interconnect structure 340B/348B formed on the second semiconductor substrate 332, and the second interconnect structure 340B/348B having a second edge interconnect feature (FIG. 3A-3B); and
a plurality of second external contacts 324B/350B formed over the second interconnect structure, wherein the first and second integrated circuit dies are positioned adjacent to each other such that the first edge conductive feature faces the second edge conductive feature (FIG. 3A-3B); and
an inter-chip connector 330C connected between the first edge conductive feature and the second edge conductive feature (FIG. 3A-3B).
Burton et al. do not disclose an encapsulant layer formed between the first integrated circuit die and the second integrated circuit die, wherein the encapsulant has a thickness equal to a height of the first integrated circuit die and an inter-chip connector embedded in the encapsulant layer and disposed between the first semiconductor substrate and the second semiconductor substrate.
Do et al. teach in Figs. 9a-9b and the related text an encapsulant layer 602 formed between the first integrated circuit die and the second integrated circuit die 200, wherein the encapsulant 602 has a thickness equal to a height of (a portion of) the first integrated circuit die 202 and an inter-chip connector 206/902 embedded in the encapsulant layer 602 and disposed between the first semiconductor substrate and the second semiconductor substrate (substrates of dies 202).
Burton et al. and Do et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Burton et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Burton et al. to include the limitations as taught by Do et al. in order to protect the semiconductor devices.
As for claim 17, Burton et al. disclose the semiconductor package of claim 15, wherein the inter-chip connector 330C is formed by an electroless deposition process prior to deposition of the encapsulate layer.
The recited limitation is drawn to a process by which the product is made. Even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product by process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. Because the product by process does not change the end product, Applicant’s claimed invention does not distinguish over prior art. See MPEP § 2113.
As for claim 19, Burton et al. and Do. Et al. disclose the semiconductor package of claim 15, wherein the first integrated circuit die comprises: a device layer 336A including one or more semiconductor devices ([0032], [0044]); and an IMD layer ILD formed over the device layer, wherein the first edge interconnect feature is formed in the IMD layer (fig. 3B).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. in view of Do et al. and further in view of Okutsu et al.
As for claim 20, Burton et al. and Do. Et al. the semiconductor package of claim 19, where the first integrated circuit die further comprises a sealing ring 21G1 in the IMD layer adjacent a perimeter of the first integrated circuit die, the sealing ring has an opening, and the first edge interconnect feature extends through the opening (fig. 12/13).
Okutsu et al. teach in Figs. 12-13 and the related text an first integrated circuit die further comprises a sealing ring 21G1 in the IMD layer adjacent a perimeter of the first integrated circuit die, the sealing ring has an opening, and the first edge interconnect feature extends through the opening (fig. 12/13).
Burton et al., Do et al. and Okutsu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Okutsu et al. in order to prevent cracks (Okutsu et al. [0007]).
Response to Arguments
Applicant’s arguments filed 10/13/2025, with respect to the rejection(s) of claim(s) 8-14 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as see above.
Applicant’s arguments, pgs. 8-9, with respect to the rejection of claim 1 that Okutsu do not teach “wherein the first integrated circuit die comprises a circuit region surrounded by a seal region, the first edge interconnect feature is formed in an IMD (inter metal dielectric) layer in the first interconnect structure and extend from the circuit region through an opening in the seal region to the first cutting surface” have been fully considered but they are not persuasive in view of the following reasons:
Okutsu et al. teach in Figs. 12-13 and the related text the first integrated circuit die 121A comprises a circuit region 21IA surrounded by a seal region 21G1 (Fig. 12), the first edge interconnect feature (left portion 27W) is formed in an IMD (inter metal dielectric) layer 25-27 in the first interconnect structure and extend from the circuit region through an opening (where left portion 27W formed in) in the seal region 21G1 to the first cutting surface (fig. 13).
Therefore, Okutsu et al. still disclose the claimed invention.
Applicant’s arguments, pgs. 14-15, with respect to the rejection of claim 15 that Burton et al. do not teach “a first integrated circuit die include a first semiconductor substrate and a second integrated circuit die includes a second semiconductor substrate” have been fully considered but they are not persuasive in view of the following reasons:
Burton et al. teach in Figs. 3B and the related text a first integrated circuit die 308A includes a first semiconductor substrate 332 ([0022], [0044]) and a second integrated circuit die 308B includes second semiconductor substrate 332 ([0022] , [0044]).
Therefore, Burton et al. still disclosed claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
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/TRANG Q TRAN/ Primary Examiner, Art Unit 2811