Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/20/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ningaraju et al. US 10096723.
Re claim 1, Ningaraju teaches a semiconductor device (fig1B) including at least one Schottky diode (SBD, fig1B, col4 line 15), comprising:
a substrate (110, fig1B, col3 line 29);
a dielectric layer (112, fig1B, col3 line 34) extending into the substrate;
a layer of polysilicon (120, fig1B, col3 line 41) disposed on the dielectric layer which electrically insulates the layer of polysilicon from the substrate;
wherein the layer of polysilicon (120, fig1B, col3 line 41) includes at least one N-type doped first cathode region (124, fig1B, col3 line 44) for the at least one Schottky diode that is adjacent to at least one undoped second anode region (126, fig1B, col3 line 44) for the at least one Schottky diode;
a first metal contact (140, fig1B, col4 line 26) disposed on a surface of said at least one N-type doped first cathode region (124, fig1B, col3 line 44);
a second metal contact (130, fig1B, col4 line 24) disposed on a surface of said at least one undoped second anode region (126, fig1B, col3 line 44); and
an electrical insulation (115, fig1B, col5 line 9) on the layer of polysilicon electrically insulating said first metal contact from said second metal contact.
Re claim 6, Ningaraju teaches a system (fig1), comprising:
a circuit configured to generate currents (current between source/drain 204 and 206, fig1B, col3 line 15-30 ) in a substrate (110, fig1B, col3 line 29); and
a semiconductor device (SBD, fig1B, col4 line 15) including at least one Schottky diode (col4 line 15);
wherein said at least one Schottky diode is coupled in parallel to the circuit (fig1A) and configured to limit currents generated by the circuit being injected in the substrate (reduce leakage current, col4 line 15-25);
wherein said semiconductor device (SBD, fig1B, col4 line 15) comprises:
a dielectric layer (112, fig1B, col3 line 34) extending into the substrate;
a layer of polysilicon (120, fig1B, col3 line 41) disposed on the dielectric layer which electrically insulates the layer of polysilicon from the substrate;
wherein the layer of polysilicon includes at least one N-type doped first cathode region (124, fig1B, col3 line 44) for the at least one Schottky diode that is adjacent to at least one undoped second anode region (126, fig1B, col3 line 44) for the at least one Schottky diode;
a first metal contact (140, fig1B, col4 line 26) disposed on a surface of said at least one N-type doped first cathode region (124, fig1B, col3 line 44);
a second metal contact (130, fig1B, col4 line 24) disposed on a surface of said at least one undoped second anode region (126, fig1B, col3 line 44); and
an electrical insulation (115, fig1B, col5 line 9) on the layer of polysilicon (120, fig1B, col3 line 41) electrically insulating said first metal contact (140, fig1B, col4 line 26) from said second metal contact (130, fig1B, col4 line 24).
Re claim 9, Ningaraju teaches a method, comprising:
forming a dielectric layer (112, fig1B, col3 line 34) in a substrate (110, fig1B, col3 line 29) so that the dielectric layer extends into the substrate;
forming a layer of polysilicon (120, fig1B, col3 line 41) on the dielectric layer, the dielectric layer configured to electrically insulate the layer of polysilicon from the substrate;
doping the layer of polysilicon to form at least one N-type doped first cathode region (124, fig1B, col3 line 44) adjacent to at least one undoped second anode region (126, fig1B, col3 line 44) of the layer of polysilicon, said at least one N-type doped first cathode region and said at least one undoped second anode region forming at least one Schottky diode (SBD, fig1B, col4 line 15);
forming a first metal contact (140, fig1B, col4 line 26) on a surface of said at least one N-type doped first cathode region (124, fig1B, col3 line 44);
forming a second metal contact (130, fig1B, col4 line 24) on a surface of said at least one undoped second anode region (126, fig1B, col3 line 44); and
electrically insulating (115, fig1B, col5 line 9) said first metal contact from and said second metal contact.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ningaraju et al. US 10096723 in view of Lee et al. US 2015/0346520.
Re claim 2, Ningaraju does not explicitly show the semiconductor device according to claim 1, wherein said electrical insulation comprises a layer of oxide extending over the layer of polysilicon between the first metal contact and said second metal contact.
Lee teaches an electrical insulation comprises a layer of oxide (350 as silicon oxide, fig3, [52]) on the layer of polysilicon electrically insulating said first metal contact from said second metal contact.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Lee to use silicon oxide as the material for Ningaraju 115. The motivation to do so is to reduce cross talk between electrodes and passivate the exposed polysilicon layer (Lee, [52]).
Re claim 7, Ningaraju does not explicitly show the system according to claim 6, wherein said electrical insulation comprises a layer of oxide extending over the layer of polysilicon between the first metal contact and said second metal contact.
Lee teaches an electrical insulation comprises a layer of oxide (350 as silicon oxide, fig3, [52]) on the layer of polysilicon electrically insulating said first metal contact from said second metal contact.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Lee to use silicon oxide as the material for Ningaraju 115. The motivation to do so is to reduce cross talk between electrodes and passivate the exposed polysilicon layer (Lee, [52]).
Re claim 10, Ningaraju does not explicitly show the method according to claim 9, wherein doping the layer of polysilicon comprises masking and etching to form openings at said at least one N-type doped first cathode region of the layer of polysilicon and ion implantation onto the layer of polysilicon at said openings.
Lee teaches doping the layer of polysilicon comprises masking and etching to form openings at said at least one N-type doped first cathode region of the layer of polysilicon (etch to form 231B, 231A and 332, fig2B, [32]) and ion implantation onto the layer of polysilicon at said openings (231 doped via ion implantation, fig2B, [36]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Lee to form the structure with the process of Lee. The motivation to do so is to achieve desired doping concentration and high speed operation (Lee, [36]).
Claim(s) 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ningaraju et al. US 10096723 in view of Hossain et al.US 2019/0115436.
Re claim 3, Ningaraju does not explicitly show the semiconductor device according to claim 1, wherein a material of the first and second metal contacts is a nickel-platinum alloy.
Hossain teaches nickel-platinum alloy used as electrodes for Schottky barrier device ([68]) to achieve lower forward voltage ([68]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Hossain to use Ni-Pt alloy as the electrode material. The motivation to do so is to achieve desired balance between forward voltage and leakage current for the device (Hossain, [68]).
Re claim 8, Ningaraju does not explicitly show the system according to claim 6, wherein a material of the first and second metal contacts is a nickel-platinum alloy.
Hossain teaches nickel-platinum alloy used as electrodes for Schottky barrier device ([68]) to achieve lower forward voltage ([68]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Hossain to use Ni-Pt alloy as the electrode material. The motivation to do so is to achieve desired balance between forward voltage and leakage current for the device (Hossain, [68]).
Claim(s) 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ningaraju et al. US 10096723 in view of Lee et al. US 2015/0346520 and Wu US 2012/0326317.
Re claim 11, Ningaraju does not explicitly show the method according to claim 9, wherein forming the first metal contact and forming the second metal contact comprises: forming a layer of oxide extending over the layer of polysilicon; etching the layer of oxide partially uncovering said at least one N-type doped first cathode region of the layer of polysilicon and said at least one undoped second anode region of the layer of polysilicon; and silicifying on a surface of said at least one N-type doped first cathode region and on a surface of said at least one undoped second anode region so that said first metal contact and said second metal contact that are insulated from each other by the layer of oxide.
Lee teaches forming the first metal contact and forming the second metal contact comprises: forming a layer of oxide (350, fig3, [52]) extending over the layer of polysilicon (332, 331, fig3, [47]); etching the layer of oxide partially uncovering said at least one N-type doped first cathode region (form opening for 361, fig3, [53]) of the layer of polysilicon (331, fig3, [47]) and said at least one undoped second anode region of the layer of polysilicon (332, fig3, [47]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Lee to use silicon oxide as the material for Ningaraju 115 and form the structure with the process of Lee. The motivation to do so is to reduce cross talk between electrodes and passivate the exposed polysilicon layer (Lee, [52]).
Wu teaches forming NiSi forming NiSi between Si and nickel-platinum alloy electrode (Wu, [7, 87]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ningaraju and Lee to use nickel-platinum alloy electrode and form a silicide. The motivation to do so is to reduce contact resistance (Wu, [3]) and improve thermal stability (Wu, [89]).
Re claim 12, Ningaraju modified above teaches the method according to one of claim 11, wherein a material of the first and second metal contacts is a nickel-platinum alloy (Wu, [87]).
Allowable Subject Matter
Claim 4-5 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to prevent steep electric field lines formed between anode and cathode of the SBD.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812