Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Miccoli et al (US 8,809,120, hereinafter Miccoli) in view of Huang et al. (US 2013/0062727, hereinafter Huang) and further in view of Sugiura (WO 2006/051866, hereinafter Sugiura).
With respect to claim 1, Miccoli discloses a method for fabricating a semiconductor device, comprising: defining a scribe line (W of Fig. 3H) on a front side of a wafer (top side of the wafer), wherein the wafer comprises an inter-metal dielectric IMD) layer on a substrate (Col. 8; lines 20-27; and Col. 10; lines 30-40);
forming a trench (327) on the front side of the wafer; performing a dicing process along the scribe line from a back side of the wafer (380 of fig. 3I).3
Miccoli does not disclose wherein a width of the trench in the IMD layer is less than a width of the scribe line; and forming a dielectric layer in the trench.
In an analogous art, Huang discloses wherein a width of the trench in the IMD layer is less than a width of the scribe line (Para 0004; 0007, 0014- crack stop trench has a width one tenth of the scribe line – the trenches penetrate the IMD layer penetrates into the substrate – Fig. 5); and forming a dielectric layer in the trench (Para 0040- forming dielectric layer 108 in the trench).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Miccoli’s disclosed invention and form dielectric layer prior to sawing the wafer from the backside to provide mechanical support to the wafer.
Miccoli/Huang does not explicitly disclose that the dicing process is followed by an expanding process to cut through the dielectric layer filled in the trench thereby dividing the dielectric layer into two portions.
In an analogous art, Sugiura discloses that the dicing process is followed by an expanding process to cut through the dielectric layer filled in the trench thereby dividing the dielectric layer into two portions (Para 0068; and 0090).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Miccoli/Huang’s disclosed invention by having Sugiura’s disclosure in order to improve the accuracy of the dicing process.
With respect to claim 3, Miccoli/Huang discloses the method of claim 1, wherein the wafer comprises: an alternating stack on the IMD layer (Miccoli; Fig. 3I).
With respect to claim 7, Miccoli/Huang discloses the semiconductor device of claim 1.
Miccoli does not disclose wherein the dielectric layer comprises silicon oxide.
In an analogous art, Huang discloses wherein the dielectric layer comprises silicon oxide (Para 0005; and 0012).
Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Miccoli’s disclosure and form the dielectric as silicon oxide as commonly known alternate in the art.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Miccoli/Huang/Sugiura in view of Kirihara et al (US 2009/0017600, hereinafter Kirihara).
With respect to claim 2, Miccoli/Huang/Sugiura disclose the method of claim 1 and performing the dicing process to divide the wafer into chips (as disclosed above).
Miccoli/Huang/Sugiura does not disclose performing a laminating process to form a tape on the front side of the wafer.
In an analogous art, Kirihara discloses performing a laminating process to form a tape on the front side of the wafer (e.g. 30 of Fig. 11).
Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Miccoli/Huang/Sugiura’s method by applying tape on the front while performing dicing to provide edges support.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Miccoli/Huang/Sugiura in view of Tao et al (US 10,937,806, hereinafter Tao).
With respect to claim 4, Miccoli/Huang/Sugiura disclose the method of claim 3.
Miccoli/Huang/Sugiura does not disclose removing the alternating stack to form the trench; and forming the dielectric layer in the trench.
In an analogous art, Tao disclose removing the alternating stack to form the trench; and forming the dielectric layer in the trench (Fig. 6 and 7).
Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Miccoli/Huang/Sugiura’s disclosed invention and form dielectric layer in the alternate stack to provide insulation.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Miccoli/Huang/Sugiura in view of Gates et al. (US 2005/0184397, hereinafter Gates).
With respect to claim 5, Miccoli/Huang/Sugiura discloses method of claim 3.
Miccoli/Huang/Sugiura does not explicitly disclose wherein the alternating stack comprises ultra low-k (ULK) dielectric layers and barrier layers alternately stacked over one another.
In an analogous art, Gates disclose wherein the alternating stack comprises ultra low-k (ULK) dielectric layers and barrier layers alternately stacked over one another (Para 0035-0036). Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Miccoli/Huang/Sugiura’s disclosed invention by having Gates’ disclosure in order to reduce RC delay in the interconnects.
Claims 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lane et al (US 8,076,756, hereinafter Lane) in view of Zhao et al. (US 2021/0159169, hereinafter Zhao).
With respect to claim 8, Lane discloses a semiconductor device (Fig. 3B), comprising: a chip (First Chip) obtained after a dicing process (separation 130), wherein the chip comprises: a stack (BEOL & FEOL) on a substrate (12); and a layer (140 - underfill) on a sidewall of the stack.
Lane does not explicitly disclose that the stack to be alternating stack or contains alternating stack structure and the layer to be dielectric layer wherein sidewalls of the dielectric layer and the substrate are aligned and the dielectric layer terminates at an interface between the alternating stack and substrate.
In an analogous art, Zhao discloses that the stack to be alternating stack or contains alternating stack structure (Para 0039-0040 – stack of alternating layers)
and the layer to be dielectric layer wherein sidewalls of the dielectric layer and the substrate are aligned (Para 0034-0035; 761 of fig. 1) and the dielectric layer terminates at an interface between the alternating stack and substrate (Fig. 1 – 761 terminates at an interface between the stack and substrate 9).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Lane’s disclosed invention and form dielectric layer as taught by Zhao to provide insulation and mechanical support.
With respect to claim 12, Lane does not disclose wherein the dielectric layer comprises silicon oxide.
In an analogous art, Zhao discloses wherein the dielectric layer comprises silicon oxide (Para 0034 – silicon oxide).
Therefore, it would have been obvious to one an ordinary skilled in the art at the time of invention to modify Lane’s disclosure and form the dielectric as silicon oxide as commonly known alternate in the art.
Claims 9 - 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lane/Zao in view of Wang et al (US 2013/0320539, hereinafter Wang).
With respect to claim 9, Lane/Zhao discloses the semiconductor device of claim 8.
Lane/Zhao does not disclose an inter-metal dielectric (IMD) layer on the substrate; and the alternating stack on the IMD layer.
In an analogous art, Wang discloses an inter-metal dielectric (IMD) layer on the substrate; and the alternating stack on the IMD layer (Fig. 1).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to Lane/Zhao’s disclosure and form the structure as taught by Wang to complete with BEOL.
With respect to claim 10, Lane discloses wherein a sidewall of the dielectric layer is aligned with a sidewall of the IMD layer (Lane; vertically aligned layer).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lane/Zhao in view of O’Brien et al (US 2007/0272666, hereinafter O’Brien).
With respect to claim 11, Lane/Zhao discloses the semiconductor device of claim 8,
Lane/Zhao does not explicitly disclose wherein the alternating stack comprises ultra low-k (ULK) dielectric layers and barrier layers alternately stacked over one another.
In an analogous art, O’Brian discloses wherein the alternating stack comprises ultra low-k (ULK) dielectric layers and barrier layers alternately stacked over one another (O’Brien; Fig. 3).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Lane/Zhao’s disclosed invention and form dielectric layer as taught by O’Brian to improve insulating properties of a semiconductor device.
Response to Arguments
Based on new ground of rejection, applicant's arguments filed on 07/28/2026 regarding claims 1-5 and 7 are moot.
Regarding claim 8, applicant argues that prior art does not explicitly disclose the amended limitation. Examiner respectfully disagrees because Zhao discloses that the stack to be alternating stack or contains alternating stack structure (Para 0039-0040 – Fig. 1 - stack of alternating layers) and the layer to be dielectric layer wherein sidewalls of the dielectric layer and the substrate are aligned (Para 0034-0035; sidewalls of 761 and 9 are aligned) and the dielectric layer terminates at an interface between the alternating stack and substrate (Fig. 1 – 761 terminates at an interface between the stack and substrate 9).
Therefore, the rejection has been maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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