Prosecution Insights
Last updated: April 19, 2026
Application No. 18/224,701

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING SUBSTRATE AND SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jul 21, 2023
Examiner
DYKES, LAURA M
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
65%
Grant Probability
Moderate
1-2
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
321 granted / 497 resolved
-3.4% vs TC avg
Strong +28% interview lift
Without
With
+27.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
42 currently pending
Career history
539
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This OA is in response to the amendment filled on 12/18/2025 that has been entered, wherein claims 1-8 and 19-26 are pending and claims 9-18 are canceled. Election/Restrictions Applicant’s election without traverse of Invention I, claims 1-8 and 19-26 in the reply filed on 12/18/2025 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 , 8, 19-24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Glenn (US 2002/0038714 A1) in view of Noh et al. (KR 19980076282 A). Regarding claim 1, Glenn teaches a method(Figs. 10 & 11, 8), comprising: mounting(Step 2) a semiconductor die(56, ¶0066) at a first surface of each die pad(24, ¶0082) of a plurality of die pads(24, ¶0082) in a semiconductor die mounting substrate(70, ¶0079), each die pad(24, ¶0082) having a second surface opposed to the first surface and further having tie bars(29, 76 between adjacent 29, ¶0083) projecting therefrom; molding(Step 4) encapsulation material(40, ¶0058) onto each semiconductor die(56, ¶0066) mounted at the first surface of each die pad(24, ¶0082) of the plurality of die pads(24, ¶0082) to form a plurality of semiconductor devices(50, Fig. 8, ¶0064) which are coupled via said tie bars(29, 76 between adjacent 29, ¶0083) projecting from the die pads(24, ¶0082); cutting(Step 5) each tie bar(29, 76 between adjacent 29, ¶0083) at an intermediate singulation location(76, ¶0083) to singulate the plurality of semiconductor devices(50, Fig. 8, ¶0064) into individual semiconductor devices(50, Fig. 8, ¶0064). Glen is not relied on to teach each tie bar(29, 76 between adjacent 29, ¶0083) has a hollowed-out portion at said intermediate singulation location(76, ¶0083), said hollowed-out portion defining a channel-shaped cross-sectional profile at said intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) wherein each tie bar(116, page 7, ¶0002) has a hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116), said hollowed-out portion(160, page 7, ¶0002) defining a channel-shaped cross-sectional profile(Fig. 6) at said intermediate singulation location(singulated end of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that each tie bar has a hollowed-out portion at said intermediate singulation location, said hollowed-out portion defining a channel-shaped cross-sectional profile at said intermediate singulation location, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 2, Glenn teaches the method of claim 1, but is not relied on to teach said hollowed-out portion is provided in a surface of each tie bar(29, 76 between adjacent 29, ¶0083) which extends from the second surface of die pad(24, ¶0082). Noh teaches a method(Fig. 6) wherein said hollowed-out portion(160, page 7, ¶0002) is provided in a surface of each tie bar(116, page 7, ¶0002) which extends from the second surface of die pad(18, Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that, said hollowed-out portion is provided in a surface of each tie bar which extends from the second surface of die pad, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 3, Glenn teaches the method of claim 1, wherein each tie bar(29, 76 between adjacent 29, ¶0083) has a length in a longitudinal direction extending away from the die pad(24, ¶0082), Glen is not relied on to teach said hollowed-out portion extends over a part of said length in said longitudinal direction. Noh teaches a method(Fig. 6) wherein said hollowed-out portion(160, page 7, ¶0002) extends over a part of said length in said longitudinal direction(Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that said hollowed-out portion extends over a part of said length in said longitudinal direction, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 4, Glenn teaches the method of claim 3, wherein each tie bar(29, 76 between adjacent 29, ¶0083) has an hourglass shape(29, 76 between adjacent 29) in said longitudinal direction with an intermediate narrowed waist portion(76 between adjacent 29, ¶0083). Glenn is not relied on to teach said hollowed-out portion is provided at said intermediate narrowed waist portion(76 between adjacent 29, ¶0083). Glen does teach the intermediate narrowed waist portion(76 between adjacent 29, ¶0083) is at intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) wherein said hollowed-out portion(160, page 7, ¶0002) is provided at said intermediate singulation location(singulated end of 116). Inserting the Noh’s hollowed-out portion into the tie bar of Glenn would result in said hollowed-out portion provided at said intermediate narrowed waist portion of Glenn. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that said hollowed-out portion is provided at said intermediate narrowed waist portion, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 6, Glenn teaches the method of claim 1, wherein the semiconductor die mounting substrate(70, ¶0079) is a ribbon substrate(70, ¶0079) comprising said plurality of die pads(24, ¶0082) distributed along a length of the ribbon substrate with each tie bar(29, 76 between adjacent 29, ¶0083) projecting from the die pad(24, ¶0082) in a direction of said length of the ribbon substrate(70, ¶0079). Regarding claim 8, Glenn teaches the method of claim 1, further comprising performing an etching operation(¶0046) to produce said intermediate singulation location(76, ¶0083). Glenn is not relied on to teach said hollowed-out portion at said intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) comprising said hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that said hollowed-out portion at said intermediate singulation location, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 19, Glenn teaches a method(Figs. 10, 11 & 8), comprising: Providing(Step 1) a leadframe(70, ¶0079) including a plurality of die pads(24, ¶0082), each die pad(24, ¶0082) having a first surface opposed to a second first surface and further having tie bars(29, 76 between adjacent 29, ¶0083) projecting from the die pad(24, ¶0082); wherein providing the leadframe(70, ¶0079) comprises providing at each tie bar(29, 76 between adjacent 29, ¶0083) at an intermediate singulation location(76, ¶0083) between die pads(24, ¶0082), mounting(Step 2) a semiconductor die(56, ¶0066) to the first surface of each die pad(24, ¶0082); encapsulating(Step 4) the leadframe(70, ¶0079) and semiconductor dies(56, ¶0066) in an encapsulation material(40, ¶0058); and singulating by cutting(Step 5) through the encapsulation material(40, ¶0058) and the tie bars(29, 76 between adjacent 29, ¶0083) at the intermediate singulation locations(76, ¶0083). Glenn is not relied on to teach providing at each tie bar(29, 76 between adjacent 29, ¶0083) a hollowed-out portion at an intermediate singulation location(76, ¶0083) between die pads(24, ¶0082), said hollowed-out portion defining a channel-shaped cross-sectional profile at said intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) wherein each tie bar(116, page 7, ¶0002) has a hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116), said hollowed-out portion(160, page 7, ¶0002) defining a channel-shaped cross-sectional profile(Fig. 6) at said intermediate singulation location(singulated end of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that each tie bar has a hollowed-out portion at said intermediate singulation location, said hollowed-out portion defining a channel-shaped cross-sectional profile at said intermediate singulation location, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 20, Glenn teaches the method of claim 19, wherein providing the leadframe(70, ¶0079) further comprises providing each tie bar(29, 76 between adjacent 29, ¶0083) with an hourglass shape(29, 76 between adjacent 29) in a longitudinal direction of the tie bar at the intermediate singulation location(76, ¶0083), said hourglass shape(29, 76 between adjacent 29) comprising an intermediate narrowed waist portion(76 between adjacent 29, ¶0083). Glenn is not relied on to teach an intermediate narrowed waist portion(76 between adjacent 29, ¶0083) located at said hollowed-out portion. Glen does teach the intermediate narrowed waist portion(76 between adjacent 29, ¶0083) is at intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) wherein is provided at said intermediate singulation location(singulated end of 116) is located at said hollowed-out portion(160, page 7, ¶0002). Inserting the Noh’s hollowed-out portion into the tie bar of Glenn would result in said hollowed-out portion provided at said intermediate narrowed waist portion of Glenn. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that an intermediate narrowed waist portion located at said hollowed-out portion, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 21, Glenn teaches a method(Figs. 10, 11 & 8), comprising: mounting(Step 2) a semiconductor die(56, ¶0066) at a first surface of each die pad(24, ¶0082) of a plurality of die pads(24, ¶0082) in a semiconductor die mounting substrate(70, ¶0079), each die pad(24, ¶0082) having a second surface opposed to the first surface and further having tie bars(29, 76 between adjacent 29, ¶0083) projecting therefrom; wherein each tie bar(29, 76 between adjacent 29, ¶0083) has: a length in a longitudinal direction extending away from the die pad(24, ¶0082); and an hourglass shape(29, 76 between adjacent 29) in the longitudinal direction of the tie bar at the intermediate singulation location(76, ¶0083), said hourglass shape(29, 76 between adjacent 29) comprising an intermediate narrowed waist portion(76 between adjacent 29, ¶0083); molding(Step 4) encapsulation material(40, ¶0058) onto each semiconductor die(56, ¶0066) mounted at the first surface of each die pad(24, ¶0082) of the plurality of die pads(24, ¶0082) to form a plurality of semiconductor devices(50, Fig. 8, ¶0064) which are coupled via said tie bars(29, 76 between adjacent 29, ¶0083) projecting from the die pads(24, ¶0082); and cutting(Step 5) each tie bar(29, 76 between adjacent 29, ¶0083) at said intermediate singulation location(76, ¶0083) through the hourglass shape(29, 76 between adjacent 29) in the longitudinal direction to singulate the plurality of semiconductor devices(50, Fig. 8, ¶0064) into individual semiconductor devices(50, Fig. 8, ¶0064). Glenn is not relied on to teach a hollowed-out portion at an intermediate singulation location(76, ¶0083); said hollowed-out portion at said intermediate singulation location(76, ¶0083) extending over a part of said length in said longitudinal direction, an intermediate narrowed waist portion(76 between adjacent 29, ¶0083) located at said hollowed-out portion. Noh teaches a method(Fig. 6) comprising a hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116), said hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116) extending over a part of said length in said longitudinal direction, said intermediate singulation location(singulated end of 116) is located at said hollowed-out portion(160, page 7, ¶0002). Inserting the Noh’s hollowed-out portion into the tie bar of Glenn would result in said hollowed-out portion provided at said intermediate narrowed waist portion of Glenn. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that a hollowed-out portion at an intermediate singulation location; said hollowed-out portion at said intermediate singulation location extending over a part of said length in said longitudinal direction, an intermediate narrowed waist portion located at said hollowed-out portion, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 22, Glenn teaches the method of claim 21, but is not relied on to teach said hollowed-out portion defines a channel-shaped cross-sectional profile open at the second surface of the die pad(24, ¶0082) at said intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) wherein said hollowed-out portion(160, page 7, ¶0002) defines a channel-shaped cross-sectional profile(Fig. 6) open at the second surface of the die pad(18, Fig. 1) at said intermediate singulation location(singulated end of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that, aid hollowed-out portion defines a channel-shaped cross-sectional profile open at the second surface of the die pad at said intermediate singulation location, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Regarding claim 24, Glenn teaches the method of claim 21, wherein the semiconductor die mounting substrate(70, ¶0079) is a ribbon substrate(70, ¶0079) comprising said plurality of die pads(24, ¶0082) distributed along a length of the ribbon substrate(70, ¶0079) with each tie bar(29, 76 between adjacent 29, ¶0083) projecting from the die pad(24, ¶0082) in a direction of said length of the ribbon substrate(70, ¶0079). Regarding claim 26, Glenn teaches the method of claim 21, further comprising performing an etching operation(¶0046) to produce said intermediate singulation location(76, ¶0083). Glenn is not relied on to teach said hollowed-out portion at said intermediate singulation location(76, ¶0083). Noh teaches a method(Fig. 6) comprising said hollowed-out portion(160, page 7, ¶0002) at said intermediate singulation location(singulated end of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Glen so that said hollowed-out portion at said intermediate singulation location, as taught by Noh, so that the tie bar is less affected by the flow of the molding resin when the molding resin is filled through the mold in the molding process of the semiconductor chip package using the lead frame resulting in lead frame having a structural stability that prevents the tie bar from bending upward, thereby causing the chip and the wire to come into contact with each other to prevent a failure in which leakage current occurs during the electrical inspection(technical task, page 5). Claims 7 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Glenn (US 2002/0038714 A1) and Noh et al. (KR 19980076282 A) as applied to claims 1 and 21 above, further in view of Yasuda et al. (US 2003/0132512 A1). Regarding claim 7, Glenn, in view of Noh, teaches the method of claim 1, but is not relied on to teach performing a coining operation to produce said hollowed-out portion at said intermediate singulation location(76, ¶0083). Yasuda teaches a method(Fig. 8) comprising performing a coining operation(¶0036) to produce said hollowed-out portion(6, ¶0062) at said intermediate singulation location(6, ¶0062). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Glen, so that performing a coining operation to produce said hollowed-out portion at said intermediate singulation location, as taught by Yasuda, to decrease burrs or to reduce wear of a punch due to the tie bar cutting operation(¶0063) Regarding claim 25, Glenn, in view of Noh, teaches the method of claim 21, but is not relied on to teach performing a coining operation to produce said hollowed-out portion at said intermediate singulation location(76, ¶0083). Yasuda teaches a method(Fig. 8) comprising performing a coining operation(¶0036) to produce said hollowed-out portion(6, ¶0062) at said intermediate singulation location(6, ¶0062). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Glen, so that performing a coining operation to produce said hollowed-out portion at said intermediate singulation location, as taught by Yasuda, to decrease burrs or to reduce wear of a punch due to the tie bar cutting operation(¶0063) Allowable Subject Matter Claims 5 and 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claims 5 and 23, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “each tie bar projects from a recessed portion of the die pad with lateral grooves located sidewise of the tie bar”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M DYKES/Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jul 21, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
65%
Grant Probability
92%
With Interview (+27.9%)
2y 10m
Median Time to Grant
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