DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-15) in the reply filed on 11/06/2025 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/06/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by You (US 2023/0187439).
Regarding claim 1, You discloses a memory device, comprising: a stack of channel layers (Fig. 2; NS1) extending vertically over a substrate (100); a gate structure (120) interleaved with the stack (NS1), wherein the gate structure (120) wraps around a first end of each channel layer (NS1) (Fig.8), the gate structure including: a dielectric layer (130) over the channel layer (NS1); a ferroelectric layer over the dielectric layer (([0063]; [0080]); and a metal layer (120) over the ferroelectric layer ([0081]); and an isolation structure (Fig. 8, numeral 160) disposed over a second end of each channel layer (NS1) opposite the first end ([0103]).
Regarding claim 2, You discloses wherein the channel layers include a doped semiconductor material ([0044).
Regarding claim 3, You discloses a first electrode (Fig.2, numeral 150) extending along a first sidewall of the stack and coupled to a third end of each channel layer (NS1); and a second electrode (150) extending along a second sidewall of the stack opposite the first sidewall and coupled to a fourth end of each channel layer opposite the third end ([0086]).
Regarding claim 4, You discloses wherein the channel layers include the doped semiconductor material ([0045]) and the isolation structure (160) is a first isolation structure, the memory device further comprising a second isolation structure (Fig.4, numeral 105) disposed between a bottom surface of the gate structure (120) and the substrate (100).
Regarding claim 7, You discloses spacers (Fig.2, numeral 140) disposed over sidewalls of the gate structure (120 between two adjacent channel layers (NS1) along a vertical direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over You as applied to claim 1 above, and further in view of Ma (US 2021/0284299).
Regarding claim 5, You does not disclose wherein the channel layers include a semiconductor material free of a dopant.
Ma however discloses wherein the channel layers include a semiconductor material free of a dopant ([0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify You with Ma to have the channel layers include a semiconductor material free of a dopant for the purpose increasing mobility (Ma, [0031]).
Regarding claim 6, You discloses wherein the isolation structure is a first isolation structure (Fig.11, numeral 160_Sw1), the memory device further comprising: a first doped semiconductor layer (Fig.2, numeral 150) disposed over a third end of each channel layer (NS1); a second doped semiconductor layer (150) disposed over a fourth end of each channel layer (NS1)opposite the third end; a first electrode (180) coupled to a top surface of the first doped semiconductor layer (150); a second electrode (180) coupled to a top surface of the second doped semiconductor layer (150); and a second isolation structure (105) disposed between a bottom surface of the gate structure (120) and the substrate (100) (Fig.4).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over You as applied to claim 1 above, and further in view of Huang (US 2023/0038782).
Regarding claim 8, You does not disclose wherein the metal layer is a first metal layer, and wherein the gate structure further includes a second metal layer disposed between the dielectric layer and the ferroelectric layer.
Huang however discloses that the metal layer is a first metal layer (Fig.6, numeral 616), and wherein the gate structure further includes a second metal layer (Fig.6, numeral 612) disposed between the dielectric layer (609) and the ferroelectric layer (614).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify You with Huang to have the metal layer is a first metal layer, and wherein the gate structure further includes a second metal layer disposed between the dielectric layer and the ferroelectric layer for the purpose of increasing a polarization in the ferroelectric layer and improving performance on a memory cell (Huang, [0022]).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over You in view of Huang.
Regarding claim 9, You discloses s semiconductor structure, comprising: a memory device, including: first channel layers (Fig.4, numerals NS1) stacked vertically over a substrate (100); a first gate structure (120) interleaved with the first channel layers (NS1), wherein the first gate structure wraps around a first end of each first channel layer (NS1), the first gate structure including: a first gate dielectric layer (130) over the first channel layer (NS1); and a second metal layer (120)over the ferroelectric layer ([0069]; [0080]); and a first dielectric layer (130) extending vertically over a second end of each first channel layer (NS1) opposite the first end.
You does not disclose a first metal layer over the first gate dielectric layer; a ferroelectric layer over the first metal layer.
Huang however discloses a first metal layer (Fig, 6, numeral 610) over the first gate dielectric layer (609); a ferroelectric layer (614) over the first metal layer (610).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify You with Huang to have a first metal layer over the first gate dielectric layer; a ferroelectric layer over the first metal layer for the purpose of increasing a polarization in the ferroelectric layer and improving performance on a memory cell (Huang, [0022]).
Regarding claim 10, You discloses wherein the first channel layers include a doped semiconductor material ([0044]).
Regarding claim 11, You discloses wherein the memory device further includes a first source/drain electrode and a second source/drain electrode coupled to a third end and a fourth end of each first channel layer (Fig.2, numeral 150), respectively, the third end and the fourth end being opposite of one another.
Regarding claim 12, You discloses wherein the first channel layers include the doped semiconductor material ([0044]), the memory device further comprising a second dielectric layer (Fig.4, numeral 105) interposed between a bottom surface of the gate structure (120) and the substrate (100).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over You and Huang as applied to claim 9 above, and further in view of Ma.
Regarding claim 13, You discloses: a first doped source/drain feature (Fig.2, numeral 150) and a second doped source/drain feature (150) coupled to a third end and a fourth end of each first channel layer (NS1), respectively, the third end and the fourth end being opposite of one another; and a second dielectric layer (1050 interposed between a bottommost first channel layer (NS1) and the substrate (100) (Fig.4).
You does not disclose wherein the first channel layers include an intrinsic semiconductor material.
Ma however discloses wherein the channel layers include an intrinsic semiconductor material ([0031]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify You with Ma to have the channel layers include an intrinsic semiconductor material for the purpose increasing mobility (Ma, [0031]).
Regarding claim 14, You discloses wherein the memory device further includes a first electrode (Fig.2, numeral 180) and a second electrode (180) coupled to the first doped source/drain feature (150) and the second doped source/drain feature (150), respectively.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over You and Huang as applied to claim 9 above, and further in view of Choi (US 2022/0310654).
Regarding claim 15, You discloses a logic device adjacent the memory device, the logic device including: second channel layers (Fig.11, numeral NS2) stacked vertically over the substrate (100); a second gate structure (220) interleaved with the second channel layers (NS2), wherein the second gate structure (220) wraps around a first end of each second channel layer (NS2), the second gate structure including: a second gate dielectric layer (230) over the second channel layer (NS2); and a third metal layer (220) over the second gate dielectric layer (230) and a second dielectric layer (160_SW2) extending vertically over a second end of each second channel layer (NS2) opposite the first end (Fig.11).
You does not disclose wherein the second gate structure is free of the ferroelectric layer.
Chou however discloses wherein the second gate structure is free of the ferroelectric layer ([0073]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify You with Choi to have the second gate structure is free of the ferroelectric layer of the purpose of fabrication a memory element and a logic element on a same die (Choi, [0190]).
Conclusion
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891