Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5, 7-11 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Verhaege et al. (Patent. No.: US 6583972 B2) or, in the alternative, under 35 U.S.C. 103 as obvious over Verhaege et al. (Patent. No.: US 6583972 B2) in view of Chen et al. (Pub. No.: US 2003/0174452 A1).
Regarding Claim 1, Verhaege et al. discloses a semiconductor device, comprising: a first metal-oxide semiconductor (MOS) transistor on a substrate (Col. 8, L 10-22, Col. 11; L 65 – Col. 12; L 35; Figs. 7, 13 etc. - first metal-oxide semiconductor (MOS) transistor 700 (see Fig. 7) (multi-finger NMOS structure)), wherein the first MOS transistor comprises: a first gate structure on the substrate (Col. 8, L 10-22, Col. 11; L 65 – Col. 12; L 35; Figs. 7, 13 etc. - first gate structure comprising G1 (see Fig. 7)); a first source/drain region adjacent to two sides of the first gate structure (Col. 8, L 10-22, Col. 11; L 65 – Col. 12; L 35; Figs. 7, 13 etc. - first source/drain comprising S1/D1 (see Fig. 7));
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a pickup region adjacent to one side of the first MOS transistor, wherein the first source/drain region and the pickup region comprise different conductive type (Col. 10, L 10-29, Col. 14, L 45 – Col. 15, L 6; Figs. 7, 10, 13, 17A-17B etc.- this prior art teaches “… the substrate connector 910 is formed by a P+ connector that is separated from the drain and source regions of the NMOS device by a ring of polysilicon. It is understood that any other P+ connector 910 to the substrate is suitable but may consume more area”); and the pickup region comprises: a first pickup doped region (please see annotated (Col. 10, L 10-29, Col. 14, L 45 – Col. 15, L 6; Figs. 7, 10, 13, 17A-17B etc.- this prior art teaches “… the substrate connector 910 is formed by a P+ connector that is separated from the drain and source regions of the NMOS device by a ring of polysilicon. It is understood that any other P+ connector 910 to the substrate is suitable but may consume more area”; a portion of the P-substrate right under 910 could be considered as the first pickup doped region); and a second pickup doped region on the first pickup doped region, wherein the first pickup doped region and the second pickup doped region comprise different concentrations (Col. 10, L 10-29, Col. 14, L 45 – Col. 15, L 6; Figs. 7, 10, 13, 17A-17B etc.- this prior art teaches “… the substrate connector 910 is formed by a P+ connector that is separated from the drain and source regions of the NMOS device by a ring of polysilicon. It is understood that any other P+ connector 910 to the substrate is suitable but may consume more area”; substrate connector 910 could be considered as the second pickup doped region);
a protection diode adjacent to another side of the first MOS transistor, wherein the protection diode is electrically connected to the first gate structure (Col. 11, L 66 -, Col. 12, L 35; Fig. 13- protection diode comprising diode D1).
In the alternative, assuming arguendo that Verhaege et al. is not emphatic enough regarding a pickup region being adjacent to one side of the first MOS transistor; and a protection diode being adjacent to another side of the first MOS transistor; Chen et al. discloses a semiconductor device, comprising: a first metal-oxide semiconductor (MOS) transistor on a substrate (Par. 0022; Fig. 4 - first metal-oxide semiconductor (MOS) transistor 140), wherein the first MOS transistor comprises:
a first gate structure on the substrate (Par. 0022-0025; Fig. 4 - first gate structure 142G; substrate 102); a first source/drain region adjacent to two sides of the first gate structure (Par. 0022-0025; Fig. 4 - first source/drain region 142S and 142D);
a pickup region adjacent to one side of the first MOS transistor, wherein the first source/drain region and the pickup region comprise different conductive type (Par. 0022-0025; Fig. 4 – pickup region comprising 148 (P+ diffusion region) and a portion of the P-substrate right under 148 (P+ diffusion region) on the right side of N+ source 142S); and the pickup region comprises: a first pickup doped region (please see annotated (Fig. 4 below - a portion of the P-substrate right under 148 (P+ diffusion region) on the right side of N+ source 142S could be considered as the first pickup doped region); and a second pickup doped region on the first pickup doped region, wherein the first pickup doped region and the second pickup doped region comprise different concentrations (Fig. 4 below - region 148 (P+ diffusion region) on the first pickup doped region on the right side of N+ source 142S could be considered as the second pickup doped region);
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a protection diode adjacent to another side of the first MOS transistor (Par. 0022-0025; Fig. 4 – protection diode 132 (the leftmost diode in Fig. 4)).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Chen et al. to adapt a semiconductor device, comprising: a pickup region of Verhaege et al. adjacent to one side of the first MOS transistor; and a protection diode adjacent to another side of the first MOS transistor in order to provide stable breakdown voltage during the ESD episode.
Regarding Claim 4, modified Verhaege et al., as applied to claim 1, discloses the semiconductor device, wherein the pickup region comprises a first conductive type (Verhaege et al. - Col. 10, L 10-29, Col. 14, L 45 – Col. 15, L 6; Figs. 7, 10, 13, 17A-17B etc.; and/or Chen et al. - Par. 0022-0024; Fig. 4 –pickup region 148 is of p-type).
Regarding Claim 5, modified Verhaege et al., as applied to claim 4, discloses the semiconductor device, wherein the protection diode comprises: a first doped region in the substrate, wherein the first doped region comprises the first conductive type (Verhaege et al. - Fig. 13; and/or Chen et al. - Par. 0022-0024; Fig. 4 – first doped region 122 of p-type conductivity); and a second doped region on the first doped region, wherein the second doped region comprises a second conductive type (Verhaege et al. - Fig. 13; and/or Chen et al. - Par. 0022-0024; Fig. 4 – second doped region 118 of n-type conductivity).
Regarding Claim 7, modified Verhaege et al., as applied to claim 4, discloses the semiconductor device, wherein the protection diode comprises: a well region in the substrate, wherein the well region comprises the first conductive type (Verhaege et al. - Fig. 13; and/or Chen et al. - Par. 0022-0024; Fig. 4 – well region 122 of p-type conductivity); and a doped region on the well region, wherein the doped region comprises a second conductive type (Verhaege et al. - Fig. 13; and/or Chen et al. - Par. 0022-0024; Fig. 4 – doped region 118 of n-type conductivity).
Regarding Claim 8, modified Verhaege et al., as applied to claim 7, discloses the semiconductor device, wherein a concentration of the well region is less than a concentration of the pickup region (Chen et al. - Par. 0023).
Regarding Claim 9, modified Verhaege et al., as applied to claim 4, discloses the semiconductor device, wherein the protection diode comprises: a first doped region in the substrate, wherein the first doped region comprises the first conductive type (Chen et al. -Par. 0022-0024; Fig. 4 – first doped region 116 of p-type conductivity); and a second doped region adjacent to the first doped region, wherein the second doped region comprises a second conductive type (Chen et al. - Par. 0022-0024; Fig. 4 – second doped region 118 of n-type conductivity).
Regarding Claim 10, modified Verhaege et al., as applied to claim 9, discloses the semiconductor device, wherein the second doped region is electrically connected to the first gate structure. (Verhaege et al. - Fig. 13).
Regarding Claim 11, modified Verhaege et al., as applied to claim 9, discloses the semiconductor device, wherein bottom surfaces of the first doped region and the second doped region are coplanar (Chen et al. - Par. 0022-0024; Fig. 4).
Regarding Claim 13, modified Verhaege et al., as applied to claim 1, discloses the semiconductor device, further comprising a second MOS transistor between the first MOS transistor and the protection diode (Chen et al. - Par. 0022-0024; Fig. 4 – second MOS transistor 110 comprising gate 112G; protection diode comprising diode 132).
Regarding Claim 14, modified Verhaege et al., as applied to claim 13, discloses the semiconductor device, wherein the first MOS transistor and the second MOS transistor comprise different conductive type (Chen et al. - Par. 0022-0024; Fig. 4).
Regarding Claim 15, modified Verhaege et al., as applied to claim 13, discloses the semiconductor device, wherein the second MOS transistor comprises: a second gate structure on the substrate (Chen et al. - Par. 0024; Fig. 4 - second gate structure 112G; substrate 102); and a second source/drain region adjacent to two sides of the second gate structure (Chen et al. - Par. 0022; Fig. 4 - second source/drain 112S and 112D).
Claim 6 is rejected under 35 U.S.C. 103 as obvious over Verhaege et al. (Patent. No.: US 6583972 B2) and Chen et al. (Pub. No.: US 2003/0174452 A1), as applied to claim 5, further in view of Pong et al. (Pub. No.: US 6835624 B2).
Regarding Claim 6, modified Verhaege et al., as applied to claim 5, does not explicitly disclose the semiconductor device, wherein a concentration of the pickup region is less than a concentration of the first doped region. However, Pong et al. at least implicitly teaches the semiconductor device, wherein a concentration of the pickup region is less than a concentration of the first doped region (Col. 4, L 65 – Col. 5, L 32 – lightly doped pickup region 150). In short, primary reference modified Verhaege et al. teaches a heavily doped pickup region with a concentration higher than a concentration of the first doped region whereas the secondary reference Pong et al. teaches a lightly doped pickup region. It is well-known that tweaking these parameters results in improvement of the device in some aspects and some deterioration in other aspects. For example, a heavily doped pickup region would lower the resistance but might result in higher leakage current. The parameters that would eventually be adapted would depend on the designer’s expectations.
Chen et al. discloses the claimed invention except for the semiconductor device, wherein a concentration of the pickup region is less than a concentration of the first doped region. It would have been an obvious matter of design choice to adapt the semiconductor device, wherein a concentration of the pickup region is less than a concentration of the first doped region, since applicant has not disclosed that this solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well wherein a concentration of the pickup region is more than a concentration of the first doped region.
Claim 12 is rejected under 35 U.S.C. 103 as obvious over Verhaege et al. (Patent. No.: US 6583972 B2) and Chen et al. (Pub. No.: US 2003/0174452 A1), as applied to claim 9, further in view of Chuang (Pub. No.: US 2013/0200488 A1).
Regarding Claim 12, modified Verhaege et al., as applied to claim 9, does not explicitly disclose the semiconductor device, further comprising a salicide block (SAB) on the first doped region. However, Chuang teaches the semiconductor device, further comprising a salicide block (SAB) on the first doped region. (Par. 0009; Fig. 3(a)). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Chuang to adapt the semiconductor device, further comprising a salicide block (SAB) on the first doped region of Chen et al. in order to prevent short circuit as taught by Chuang (Par. 0009).
Response to Arguments
Applicants’ arguments filed on 07/02/2026 have been fully considered but they are not found to be persuasive. Please see the rejections above for detailed explanation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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07/18/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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