DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Status of the Claims
Amendment filed February 19, 2026 is acknowledged. New Claims 57-59 have been added. Claims 30, 40 and 50 have been cancelled. Claims 24, 32-34, 42-44 and 52-53 have been amended. Claims 24, 27-29, 31-34, 37-39, 41-44 and 47-49, 51-59 are pending.
Action on merits of the Elected Species, claims 24, 27-29, 31-34, 37-39, 41-44 and 47-49, 51-59 follows.
Double Patenting
The Applicant requested that the double patenting rejection of Claims 24, 30, 34, 40, 44 and 50, imposed in the OFFICE ACTION mailed March 12, 2025, be held in abeyance until an indication of allowable subject matter is made in the present application.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 24, 28-29, 31-34, 38-39, 41-44, 48-49, 51-53, and 57-59 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over YAMAZAKI et al. (US. Patent No. 6,127,702) in view of SUGIHARA et al. (US. Pub. No. 2006/0244107) both of record.
With respect to claim 24, YAMAZAKI ‘702 teaches a semiconductor device substantially as claimed including:
a first transistor (upper right) and a second transistor (lower left),
wherein one of a source and a drain (1922) of the first transistor is electrically connected to a gate electrode (1928) of the second transistor,
wherein the first transistor comprises a channel formation region (1926) in a semiconductor layer,
wherein the second transistor comprises a channel formation region in a silicon region,
wherein the semiconductor layer does not overlap with the gate electrode (1928) of the second transistor, and
wherein the first transistor having an off-state current. (See FIG. 19B).
Thus, YAMAZAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the channel formation region of the first transistor utilizing an oxide semiconductor layer; and an off-state current of the first transistor is 1x10-13 A or less.
However, SUGIHARA teaches a semiconductor device including a first transistor (1), wherein the first transistor (1) comprises a channel formation region in an oxide semiconductor layer (5), wherein an off-state current of the first transistor is 1x10-13 A or less. (See FIGs. 1, 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first transistor of YAMAZAKI utilizing channel formation region in the oxide semiconductor layer as taught by SUGIHARA to provide for the transistor having good property and low off current even when prepared under low temperature.
Transistor utilizing oxide-semiconductor is well-known in the art to be a good substitute for silicon semiconductor for the same intended purpose.
Further, it has been held to be within the general skill of a worker in the art to select a known material, silicon or oxide semiconductor, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 34, YAMAZAKI teaches a semiconductor device substantially as claimed including:
a first transistor (upper right) and a second transistor (lower left),
wherein one of a source and a drain (1922) of the first transistor is electrically connected to a gate electrode (1928) of the second transistor,
wherein the first transistor comprises a channel formation region (1926) in a semiconductor layer,
wherein the second transistor comprises a channel formation region in a silicon region,
wherein the semiconductor layer does not overlap with the gate electrode (1928) of the second transistor, and
wherein the first transistor having an off-state current,
wherein a potential is supplied to the gate electrode (1928) of the second transistor by turning on the first transistor, and
wherein the potential of the gate electrode (1928) of the second transistor is held by turning off the first transistor. (See FIG. 19B).
Thus, YAMAZAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the channel formation region of the first transistor utilizing an oxide semiconductor layer; and an off-state current of the first transistor is 1x10-13 A or less.
However, SUGIHARA teaches a semiconductor device including a first transistor (1), wherein the first transistor (1) comprises a channel formation region in an oxide semiconductor layer (5), wherein an off-state current of the first transistor is 1x10-13 A or less. (See FIGs. 1, 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first transistor of YAMAZAKI utilizing channel formation region in the oxide semiconductor layer as taught by SUGIHARA to provide for the transistor having good property and low off current even when prepared under low temperature.
Transistor utilizing oxide-semiconductor is well-known in the art to be a good substitute for silicon semiconductor for the same intended purpose.
Further, it has been held to be within the general skill of a worker in the art to select a known material, silicon or oxide semiconductor, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Regarding the limitations: “wherein a potential is supplied to the gate electrode of the second transistor by turning on the first transistor, and wherein the potential of the gate electrode of the second transistor is held by turning off the first transistor” are the functions or characteristics of the semiconductor device, where one of source or drain of the first transistor being connected to the gate of the second transistor.
Since the semiconductor device of YAMAZAKI comprising the same connections, the semiconductor device of YAMAZAKI is fully capable of the same functions.
With respect to claim 44, YAMAZAKI teaches a semiconductor device substantially as claimed including:
a first transistor (NFET) and a second transistor (PFET),
wherein one of a source and a drain (1922) of the first transistor is electrically connected to a gate electrode (1928) of the second transistor,
wherein the first transistor comprises a channel formation region (1926) in a semiconductor layer,
wherein the second transistor comprises a channel formation region in a silicon region,
wherein the semiconductor layer does not overlap with the gate electrode (1928) of the second transistor, and
wherein the first transistor having an off-state current. (See FIG. 19B).
Thus, YAMAZAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the channel formation region of the first transistor utilizing an i-type or substantially i-type oxide semiconductor layer; and an off-state current of the first transistor is 1x10-13 A or less.
However, SUGIHARA teaches a semiconductor device including a first transistor (1), wherein the first transistor (1) comprises a channel formation region in an oxide semiconductor layer (5), wherein the oxide semiconductor layer (5) comprises a region being i-type or substantially i-type, wherein an off-state current of the first transistor is 1x10-13 A or less. (See FIGs. 1, 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first transistor of YAMAZAKI utilizing channel formation region in the oxide semiconductor layer, comprising the region being i-type or substantially i-type, as taught by SUGIHARA to provide for the transistor having good property and low off current even when prepared under low temperature.
Transistor utilizing oxide-semiconductor is well-known in the art to be a good substitute for silicon semiconductor for the same intended purpose.
Further, it has been held to be within the general skill of a worker in the art to select a known material, silicon or oxide semiconductor, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claims 28, 38 and 48, in view of SUGIHARA, the oxide semiconductor layer (5) comprises a mixture of polycrystalline and amorphous portion, hence a microcrystalline.
With respect to claims 29, 39 and 49, in view of SUGIHARA, the off-state current of the first transistor (1) is 1x10-13 A or less when a drain voltage is +1 V or +10 V and a gate voltage ranges from -20 V to -5 V.
With respect to claims 31, 41 and 51, in view of SUGIHARA, the oxide semiconductor layer (5) comprises one of an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-AI-Zn-O-based oxide semiconductor, a Sn-Ga-Zn-O-based oxide semiconductor, an AI-Ga-Zn-O-based oxide semiconductor, a Sn-AI-Zn-O-based oxide semiconductor, an In-Zn-O-based oxide semiconductor, a Sn-Zn-O-based oxide semiconductor, an AI-Zn-O-based oxide semiconductor, an In-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, and a Zn-O-based oxide semiconductor.
With respect to claims 32, 42 and 52, the semiconductor device of YAMAZAKI, in view of SUGIHARA, can be used as a memory element comprising a gate wiring, and wherein the gate wiring is electrically connected to a gate electrode (1925) of the first transistor.
With respect to claims 33, 43 and 53, the semiconductor device of YAMAZAKI, in view of SUGIHARA, can be used as a non-volatile memory element comprising a gate wiring, wherein the gate wiring is electrically connected to a gate electrode (1925) of the first transistor, and wherein the non-volatile memory element is configures to hold data.
With respect to claims 57-59, in view of SUGIHARA, the oxide semiconductor layer (5) is crystallized.
The expression “the oxide semiconductor layer is crystallized” is taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Note that Applicant has burden of proof in such cases as the above case law makes clear.
Since the oxide semiconductor layer of SUGIHARA comprising polycrystalline, the limitation “is crystallized” is met.
Claims 27, 37, 47 and 54-56 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over YAMASZAKI ‘702 and SUGIHARA ‘107 as applied to claims 24, 34 and 44 above, and further in view of IWASAKI (US. Pub. No. 2009/0045397) of record.
With respect to claims 27, 37 and 47, YAMAZAKI, in view of SUGIHARA, teaches the semiconductor device as described in claims 24, 34 and 44 above including: the first transistor comprising the channel formation region in the oxide semiconductor layer having a hydrogen concentration.
Thus, YAMAZAKI and SUGIHARA are shown to teach all the features of the claim with the exception of explicitly disclosing the hydrogen concentration in the oxide semiconductor layer.
However, IWASAKI teaches a semiconductor device including:
a first transistor (TFT) comprising the channel formation region in an oxide semiconductor layer (11), wherein a hydrogen concentration measured by SIMS in the oxide semiconductor layer (11) is 1019 atoms/cm3 or less. (See FIGs. 1A-B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first transistor of YAMAZAKI, in view of SUGIHARA, having the hydrogen concentration of 1019 atoms/cm3 or less as taught by IWASAKI to provide for a normally off transistor of high ON/OFF ratio.
With respect to claims 54-56, in view of IWASAKI, the oxide semiconductor layer (11) comprises an In-O-based oxide semiconductor.
Response to Arguments
Applicant’s arguments with respect to claim(s) February 19, 2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893