DETAILED ACTION
Response to Arguments
In light of applicant’s amendments to the drawings, specification, and the claims the objections are hereby withdrawn.
Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive.
Applicant argues on page 9 of the remarks that Chung does not teach all of the features of claim 1 and in particular that Chung does not teach “a plurality of gate structures of each of which gate structure of the plurality of gate structures surrounds multiple semiconductor nanosheets of the plurality of stacked semiconductor nanosheets.”
Examiner respectfully disagrees. Applicant cited Fig. 23 of the Chung reference which does not clearly show the claimed features. Below is an edited version of Fig. 21B beside applicant’s edited Fig. 1C which show the gates surrounding the plurality of nanosheets.
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As can be seen in edited Fig. 21B, Chung shows a plurality of gate structures, i.e., G1 and G2, which surround multiple semiconductor nanosheets of the stacked semiconductor nanosheets, i.e., channels, in Fig. 21B. Edited Fig. 21B shows gate G1 and G2 surrounding channels 204C, 204B, and 204A wherein the gate “arms” or extensions are vertically adjacent.
Applicant also argues on page 10 of the Remarks that Chung does not teach all of the features of claim 20 for the same reasons as noted with respect to claim 1. Therefore, as discussed in the response for claim 1, the arguments are not persuasive.
Regarding claims 11 and 12, Applicant argues on page 11 of the Remarks that by virtue of their dependencies on claim 1 they are in condition for allowance. Given the arguments provided by Examiner regarding claim 1, the rejection for claims 11 and 12 are maintained.
Regarding claims 13-17 and 19, Applicant argues on page 11 that Lin does not teach all of the features of claim 13. In light of applicant’s amendment to claim 13, a new ground of rejection will be applied.
Furthermore, applicant argues on page 12 that “there is no teaching, whatsoever, that the back gate metal 40 is between a pair of the plurality of stacked semiconductor nanosheets.” and that the arrangement provided “would not be possible due to the fact that the back gate metal 40 is provided as a core along an entire vertical extent to the tubular vertical channel structures (e.g., nanosheets).”
Examiner would like to note that claim 13 does not disclose any specific details regarding the “back gate bias material” and therefore, given the broadest reasonable interpretation, may be interpreted as a “material between the pair of the plurality of stacked semiconductor nanosheets.”
Applicant does not provide additional arguments regarding claims 14-19 other than citing their dependencies on previously argued claims.
Claim Objections
Claim 13 is objected to because of the following informalities: lines 4-5 state “and conductive material with alternates with each gate structure…” It appears the claim should state “and conductive material which alternates with each gate structure…”
Appropriate correction is required.
Claim Interpretation
Claim 13 discloses the following: and a back gate bias material between the pair of the plurality of stacked semiconductor nanosheets.
Paragraph [0021] of the applicant’s specification discloses:
[0021] The different materials 24 may include a conductive material 24 a surrounded by an insulator material 24 b. In embodiments, the conductive material 24 a may be Si or polysilicon material; whereas the insulator material 24 b may be an oxide material (e.g., SiO2). It should be understood by those of skill in the art that other conductive material and insulator material may be used for the materials 24 a, 24 b. For example, the material 24 a may be a metal or metal alloy. In embodiments, the conductive material 24 a may be used to provide a back gate bias to the gate structures 22. (Emphasis mine)
Therefore, given the broadest reasonable interpretation, the back gate bias material may be interpreted as a metal or metal alloy.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 13-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHUNG et al. (US 20230029046 A1, cited in prior office action), hereinafter “Chung.”
Re: Independent Claim 1, Chung discloses a structure comprising (See Figs. 21B and 22B):
a plurality of stacked semiconductor nanosheets over a semiconductor substrate (Fig. 21B: channels 204A-C and semiconductor substrate 200);
a plurality of gate structures comprising vertically adjacent gate structures which surround multiple semiconductor nanosheets of the plurality of stacked semiconductor nanosheets (Fig. 21B: Gates G1 and G2 have extensions, e.g., red and blue lines shows in the edited Fig. 21B, that are vertically adjacent and surround channels 204C, 204B, and 204A.; See edited Fig. 21B below);
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a conductive material between the plurality of stacked semiconductor nanosheets and the plurality of gate structures (Fig. 21B: G2 gate fill metal 228 and G1 gate fill metal 220 as shown in Fig. 18C; ¶0105: In some other embodiments, the gate fill metal 228 has a different metal from the gate fill metal 220 of the first gate structure 210.; ¶0099: the gate fill metal 220 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.);
an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material (Fig. 22B shows inner spacers (not labeled) next to gates 210 and 212; See Fig. 23 which labels said spacers as 232); and
source/drain regions 32 on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer (Fig. 22B: S/D regions 208 on opposing sides of the plurality of gate structures 210 and 212 which are separated therefrom by inner sidewall spacer; ¶0062: epitaxial source and drain (collectively referred to as source/drain or S/D in the present disclosure) regions 208 disposed on the fin 202 and on opposite ends of the channel layers 204.).
Re: Claim 2, Chung discloses the structure of claim 1, and
further comprising a first contact electrically connecting to the plurality of gate structures and a second contact electrically connecting to the conductive material (Fig. 21B shows a first contact G1 which connects to the gate structures 210, 212, and 210 as shown in Fig. 22B; Fig. 18B shows a high-k dielectric layer 216 and gate fill metal 220 which connect to the plurality of gate structures; Fig. 21B further shows a second contact G2 which includes a gate fill metal 228 which electrically connects to conductive material).
Re: Claim 3, Chung discloses the structure of claim 2, and
wherein the first contact electrically connects to the plurality of gate structures from a first side and the second contact electrically connects to the conductive material from a second side (Fig. 21B shows a first gate contact G1 on the left side, i.e., first side, and a second gate contact G2 on the right side, i.e., second side).
Re: Claim 4, Chung discloses the structure of claim 3, and
wherein the plurality of gate structures and the conductive material are tiered (Fig. 21B shows a first gate contact G1 a second gate contact G2 along with channels 204A-C. The Gate structures have extensions which form vertically adjacent structures, i.e., tiered. See edited Fig. 21B above.).
Re: Claim 5, Chung discloses the structure of claim 1, and
wherein the plurality of gate structures comprise a gate dielectric material and a gate body comprising polysilicon material (Fig. 18B shows a high-k dielectric layer 216 and gate fill metal 220 which connect to the plurality of gate structures; Fig. 21B further shows a second contact G2 which includes a gate fill metal 228 which electrically connects to conductive material; ¶0084: The dummy gate structure 308 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon); ¶0132: In some embodiments where the dummy gate structure 604 is formed of polysilicon, the gate-cut opening 607 can be referred to as cut polysilicon (CPO) regions that cut the polysilicon gates).
Re: Claim 6, Chung discloses the structure of claim 1, and
wherein the plurality of gate structures comprise a gate high-k dielectric material and a gate body comprising a workfunction metal (Fig. 18C shows a high-k dielectric layer 216 and a work function metal layer 218; ¶0063: The first gate structure 210 includes a… high-k dielectric layer 216 … a work function metal layer 218 over the high-k dielectric layer 216, and a gate fill metal 220 over the work function metal layer 218).
Re: Claim 7, Chung discloses the structure of claim 1, and
wherein the plurality of gate structures surround a pair of the plurality of stacked semiconductor nanosheets and the pair of the stacked semiconductor nanosheets surrounds a single level of the conductive material (Fig. 21B shows gate structures G1 and G2 surrounding a pair of nanosheets, i.e., channels 204C and 204B, of the plurality of nanosheets 204A, 204B, and 204C.; Furthermore, channels 204C and 204B, i.e., a pair, surround the upper extension of the G1 gate, i.e., single level of G1 which has a gate fill metal 202; Channels 204A and 204B surround the lower extension “S3” of gate G2 which has conductive material/gate fill metal 228).
Re: Claim 8, Chung discloses the structure of claim 7, and
wherein the conductive material is surrounded by a dielectric material contacting the vertically adjacent stacked semiconductor nanosheets of the plurality of stacked semiconductor nanosheets (Fig. 21B shows gates G1 and G2 wherein G1 and G2 are surrounded by a dielectric material; Fig. 18B shows conductive material 220, i.e., gate fill metal 220 of gate G1, surrounded by a dielectric material 216 contacting channels 204A, 204B, and 204C as shown in Fig. 21B).
Re: Claim 9, Chung discloses the structure of claim 1, and
wherein the plurality of stacked semiconductor nanosheets comprise silicon on insulator material (¶0079: In some embodiments, the second semiconductor layers 204A-204C (collectively referred to as second semiconductor layers 304) are formed of a second semiconductor material. In some embodiments, the second semiconductor material is silicon.).
Re: Claim 10, Chung discloses the structure of claim 1, and
wherein the plurality of gate structures comprise wraparound gate structures (See Fig. 21B which shows gates G1 and G2 which wrap around channels 20A, 204B, and 204C; ¶0060: a gate-all-around (GAA) transistor that comprises channel layers 204A-C over a fin 202 on a substrate 200, wherein the channel layers 204A-C (collectively referred to as channel layers 204) act as channel regions).
Re: Independent Claim 13, Chung discloses a structure comprising (See Figs. 21B and 22B):
a plurality of stacked semiconductor nanosheets (Fig. 21B: channels 204A-C);
a plurality of gate structures comprising vertically adjacent gate structures which surround a pair of the plurality of stacked semiconductor nanosheets and conductive material with alternates with each gate structure of the plurality of gate structures (Fig. 21B: Gates G1 and G2 comprising vertically adjacent gate extensions, i.e., structures, which surround a pair of nanosheets; Fig. 21B: G2 gate fill metal 228 and G1 gate fill metal 220 as shown in Fig. 18C; ¶0105: In some other embodiments, the gate fill metal 228 has a different metal from the gate fill metal 220 of the first gate structure 210, i.e., alternates with each gate structure; ¶0099: the gate fill metal 220 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.); and
a back gate bias material between a pair of the plurality of stacked semiconductor nanosheets. (Note: there are no details claimed regarding what the back gate bias material is. Given the broadest reasonable interpretation, a back gate bias material may be any material such as a metal or metal alloy; ¶0099: In some other embodiments, the gate fill metal 220 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials; ¶0105: gate fill metal 228 has a different metal from the gate fill metal 220 of the first gate structure 210).
Re: Claim 14, Chung discloses the structure of claim 13, and
wherein the plurality of stacked semiconductor nanosheets comprise Si material (¶0079: the second semiconductor layers 204A-204C (collectively referred to as second semiconductor layers 304) are formed of a second semiconductor material. In some embodiments, the second semiconductor material is silicon.).
Re: Claim 15, Chung discloses the structure of claim 13, and
wherein the plurality of gate structures comprise a gate dielectric material wrapping around the pair of the plurality of stacked semiconductor nanosheets and a conductive gate body (Fig. 21B shows gates G1 and G2 wherein G1 and G2 are surrounded by a dielectric material; Fig. 18B shows conductive material 220, i.e., gate fill metal 220 of gate G1, surrounded by a dielectric material 216 contacting channels 204A, 204B, and 204C as shown in Fig. 21B).
Re: Claim 16, Chung discloses the structure of claim 13, and
wherein the back gate bias material comprises the conductive material wrapped by an insulator material (See Fig. 21B; ¶0063: The first gate structure 210 includes an interfacial layer 214, a high-k dielectric layer 216 over the interfacial layer 214, a work function metal layer 218 over the high-k dielectric layer 216, and a gate fill metal 220 over the work function metal layer 218. The second gate structure 212 also includes an interfacial layer 222, a high-k dielectric layer 224 over the interfacial layer 222, a work function metal layer 226 over the high-k dielectric layer 224, and a gate fill metal 228 over the work function metal layer 226. The first and second gate structures 210 and 212 are electrically isolated by the interfacial layers 214, 222, and the high-k dielectric layers 216, 224, and thus the first and second gate structures 210 and 212 can serve as two independent gate terminals G1 and G2 that are independently controlled).
Re: Claim 17, Chung discloses the structure of claim 13, and
wherein the vertically adjacent gate structure of the plurality of gate structures comprise two gate structures (Fig. 21B shows vertically adjacent gate structures above and below channels 204A-C; See Fig. 21A; ¶0062: first gate structure 210 and a second gate structure 212).
Re: Independent Claim 20, Chung discloses a method comprising:
forming a plurality of stacked semiconductor nanosheets over a semiconductor substrate (Fig. 11B shows stacked semiconductor nanosheets over a substrate 200; ¶0081: The first semiconductor layers 302, the second semiconductor layers 204, and the third semiconductor layers 304 may be formed by one or more epitaxy or epitaxial (epi) processes. The epitaxy processes include CVD deposition techniques; ¶0082: After the epitaxial growth process of the layer stack is complete, a patterning process is performed on the layer stack to form a fin structure FS, as illustrated in FIGS. 11A and 11B.);
forming a plurality of gate structures comprising vertically adjacent gate structures which surround multiple semiconductor nanosheets of the plurality of stacked semiconductor nanosheets (Fig. 21B: Gates G1 and G2 have extensions that are vertically adjacent and surround channels 204C, 204B, and 204A.; See edited Fig. 21B below; Fig. 17B shows the formation process of gate structures S1 and S2 surrounding the channels 204A, 204B and 204C; ¶0095: In FIGS. 17A and 17B, a selective etching process is performed to selectively etch the first sacrificial layers 302 exposed in the opening 312 of the patterned mask 310.);
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forming a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures (Fig. 18B shows deposition of materials 214, 216, 218, and 220 between the plurality of the channels and the plurality of gate structures; See Fig. 21B; 0063: The first gate structure 210 includes an interfacial layer 214, a high-k dielectric layer 216 over the interfacial layer 214, a work function metal layer 218 over the high-k dielectric layer 216, and a gate fill metal 220 over the work function metal layer 218. The second gate structure 212 also includes an interfacial layer 222, a high-k dielectric layer 224 over the interfacial layer 222, a work function metal layer 226 over the high-k dielectric layer 224, and a gate fill metal 228 over the work function metal layer 226.);
forming an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material (Fig. 23 shows spacers 232 adjacent to the gate structures 210 which includes conductive material, i.e., gate fill metal 220, as shown in Fig. 18B; ¶0090: inner spacers 232); and
forming source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer (Fig. 22B shows source/drain regions 208 on opposing sides of the gate structures separated by inner spacers; ¶0064: Inner spacers 232 are disposed vertically between adjacent two of the channel layers 204 and the fin 202, as illustrated in the cross-sectional view in FIG. 10B. The gate spacers 230 and inner spacers 232 may serve to electrically isolate the first, second gate structures 210, 212 from the epitaxial source/drain regions 208.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (US 20230029046 A1) in view of ZOTA et al. (US 20220302269 A1), hereinafter “Zota.”
Re: Claim 11, Chung discloses the structure of claim 1.
However, Chung does not specifically disclose wherein the plurality of gate structures comprise one of an NFET and a PFET.
In a similar field of endeavor, Zota discloses wherein the plurality of gate structures comprise one of an NFET and a PFET (Fig. 12 shows another embodiment in which two gate stacks are implemented; ¶0049: n-FET/p-FET stacked device structures).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, in order to allow for the dense heterogeneous integration of stacked nanosheet n-MOS and p-MOS, a technology which may also be used for TFETs (See Zota, ¶0047).
Re: Claim 12, Chung discloses the structure of claim 1.
However, Chung does not specifically disclose wherein the plurality of gate structures comprise an NFET and a PFET, separated by an insulator material.
In a similar field of endeavor, Zota discloses wherein the plurality of gate structures comprise an NFET and a PFET, separated by an insulator material (See Fig. 12; ¶0049: n-FET/p-FET stacked device structures; ¶0083: FIG. 12 shows an alternative embodiment 1200 with separated source and drain regions for the transistors. The insulation layer 1202 ensures that the respective source and drain regions are not connected to each other.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, in order to allow for the dense heterogeneous integration of stacked nanosheet n-MOS and p-MOS, a technology which may also be used for TFETs (See Zota, ¶0047).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG et al. (US 20230029046 A1) in view of LEE et al. (US 20170345946 A1), hereinafter “Lee.”
Re: Claim 18, Chung discloses the structure of claim 13.
However, Chung does not disclose further comprising a semiconductor nanosheet below a bottommost gate structure of the plurality of gate structures.
In a similar field of endeavor, Lee discloses further comprising a semiconductor nanosheet below a bottommost gate structure of the plurality of gate structures (See Fig. 5: nanosheet 124; Fig. 8 shows a nanosheet 224 below a bottommost gate; ¶0050: The fourth nanosheet 124 may be on an upper surface of the substrate 101; ¶0036: The number and a disposition of the nanosheets 120 are not limited to the configuration of FIG. 3, and may be variously changed.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure in Chung to include additional nanosheets as disclosed by Lee in order to increase the number of channels available (See Lee, ¶0036).
Re: Claim 19, Chung discloses the structure of claim 13.
Chung further discloses wherein:
…
the plurality of gate structures comprise at least three gate structures each of which surround a pair or the plurality of stacked semiconductor nanosheets (Fig. 22B: Gates 210, 212, and 210; Gates 210 and 212 surround channel 204B while gates 212 and 210 surround channel 204A wherein channels 204B and 204A may be considered a pair), with a common semiconductor nanosheet being shared with one of the gate structures of the at least three gate structures (Fig. 22B: channel 204A, i.e., nanosheet, is shared between gates 212 and 210); and
the back gate bias material comprises two different layers between a respective pair of the plurality of stacked semiconductor nanosheets (Fig. 22B: channel 204A, i.e., nanosheet, is between two gates 212 and 210; Each gate 210, 212, and 210 may comprise a different gate fill metals, i.e., two different layers of material; ¶0099: In some other embodiments, the gate fill metal 220 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials; ¶0105: gate fill metal 228 has a different metal from the gate fill metal 220 of the first gate structure 210).
However, Chung does not specifically disclose the plurality of stacked semiconductor nanosheets comprise at least four nanosheets;
In a similar field of endeavor, Lee discloses the plurality of stacked semiconductor nanosheets comprise at least four nanosheets (Fig. 5: nanosheets 120 include a fourth nanosheet 124; ¶0036: The number and a disposition of the nanosheets 120 are not limited to the configuration of FIG. 3, and may be variously changed.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure in Chung to include additional nanosheets as disclosed by Lee in order to increase the number of channels available (See Lee, ¶0036)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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