DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges the amendments to claims 1, 13, and 20 in the reply dated 10 April 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al (US 20210249394 A1, hereinafter “Ikeda”), in view of Kim et al (US 20190206971 A1, hereinafter “Kim”), and further in view of Na et al (US 20200168147 A1, hereinafter “Na”).
Regarding Claim 13 – Ikeda discloses a light emitting display device, comprising: a driving transistor (DRT [0065] and Fig. 3) including a first gate electrode (64 [0065] and Fig. 5) and a first semiconductor (61 [0065] and Fig. 5); a second transistor (SST [0070] and Fig. 3) including a second gate electrode (78 [0070] and Fig. 5), and a second semiconductor (75 [0070] and Fig. 5) having one end connected to a data line (L2 [0050] and Fig. 3) and another end connected to the first gate electrode of the driving transistor (DRT gate coupled to drain of SST [0047] and Fig. 3); a light emitting diode including an anode (3 including 23t [0046] and Fig. 5); and a storage capacitor including a first storage electrode (61a [0066] and Fig. 5) connected to the anode of the light emitting diode (61a connected to 23t via 62, 24, and 23 in Fig. 5) and a second storage electrode (64 [0066] and Fig. 5) overlapping the first storage electrode in a plan view (61a overlapping 64 in Fig. 4).
Ikeda fails to disclose the first gate electrode does not overlap the first storage electrode or the second storage electrode in a plan view.
However, Kim discloses the first gate electrode (122 Kim [0065] and Fig. 5A) does not overlap the first storage electrode (108 and 120 Kim [0083] and Fig. 5A) or the second storage electrode (130 Kim [0106] and Fig. 5A) in a plan view (No overlap in Figs. 4 and 5A).
Kim discloses an analogous display device to Ikeda. Kim teaches the first gate electrode does not overlap the first storage electrode to enable via connection to the gate electrode, since the gate electrode (122) and the storage capacitor electrodes (108, 120, and 130) are on different layers and layer 130 connects the gate electrode to other circuit features (Kim [0071] and Fig. 5A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to not overlap the first gate electrode and the storage electrodes to enable the use of a via to connect to the first gate electrode.
Ikeda fails to disclose a shielding member overlapping the data line, the shielding member has a wider width than the data line at an overlapping portion of the shielding member and the data line in a plan view, so all parts of the data line at the overlapping portion of the shielding member and the data line are disposed inside of the shielding member in a plan view.
However, Na discloses a shielding member overlapping the data line (M overlaps 171, Na [0082] and Fig. 1), the shielding member has a wider width than the data line at an overlapping portion of the shielding member and the data line in a plan view, so all parts of the data line at the overlapping portion of the shielding member and the data line are disposed inside of the shielding member in a plan view (Shield member M overlaps 171 including beyond the width of 171 where they overlap, Na Fig. 1).
Na discloses a similar display circuit to Ikeda. Na teaches overlapping the data line with a shield member for the benefit of reducing the influence of data line signal transmission on the compensation transistor to reduce power consumption and improve display quality (Na [0075] and [0156]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Ikeda and Na to overlap a data line with a shield member for the benefit of reducing the influence of data line signal transmission on the compensation transistor to reduce power consumption and improve display quality.
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Regarding Claim 14 – Ikeda modified by Kim and Na discloses all the limitations of claim 13.
The combination of Ikeda, Kim, and Na further discloses a hold capacitor (Cs2 Ikeda [0044] and Fig. 3) including a first electrode (L1 Ikeda [0046] and Fig. 3) and a second electrode (23 Ikeda [0046] and Fig. 3), wherein the second electrode of the hold capacitor is integral with the first storage electrode (electrically connected through 62 and 24 as in Ikeda Fig. 5), the first electrode of the hold capacitor and the second storage electrode overlap in a plan view (Overlap can be seen in Ikeda Fig. 5), the first gate electrode does not overlap the first electrode of the hold capacitor in a plan view (122 does not overlap 108, 120, or 130 in Kim Figs. 4 and 5), and the first electrode of the hold capacitor is connected to a driving voltage line or a reference voltage line (L1 Ikeda [0055] and Fig. 3).
Regarding Claim 15 – Ikeda modified by Kim and Na discloses all the limitations of claim 13.
The combination of Ikeda, Kim, and Na further discloses a first scan line (L7 Ikeda [0036] and Fig. 3) connected to the second gate electrode of the second transistor (Gate of SST Ikeda [0050] and Fig. 3); and a driving gate electrode connecting member (L9 Ikeda [0058] and Figs. 4 and 5) connecting the second semiconductor of the second transistor, the second storage electrode, and the first gate electrode of the driving transistor (Ikeda Figs. 4 and 5), wherein the first scan line and the driving gate electrode connecting member cross and overlap in a plan view (Cross in annotated Ikeda Fig. 4), and the driving gate electrode connecting member are positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor (L9 in a different layer from 61, 75, 64, an 78 Ikeda [0060] and Fig. 5).
Ikeda fails to disclose the first scan line is positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor.
However, Kim discloses the first scan line (173 Kim [0074] and Fig. 5A) is positioned on a different layer from the first gate electrode (122 Kim[0065] and Fig. 5A), the second gate electrode (132 Kim [0074] and Fig. 5A), the first semiconductor (120c Kim [0064] and Fig. 5A), and the second semiconductor (130c Kim [0070] and Fig. 5A).
Kim discloses a display circuit analogous to Ikeda. Kim teaches the scan (gate) line may be in a different layer than the gate electrodes, which is a case of simple substitution of one existing conductive layer for another to provide a circuit path for the scan line, and the conductive layers are all known to carry electrical signals. This simple substitution of one conductive layer for another presents a prima facie case of obviousness. See MPEP 2143(I)(B). Therefore, it would have been obvious prior to the effective filing date to consider combining the teachings of Ikeda and Kim to use a simple substitution of a different conductive layer than the gate electrode and semiconductor layers for the scan line because any of the conductive layers can carry electrical signals.
Regarding Claim 16 – Ikeda modified by Kim and Na discloses all the limitations of claim 15.
The combination of Ikeda, Kim, and Na further discloses a third transistor (IST Ikeda [044] and Fig. 3) including a third gate electrode (L8 Ikeda [0068] and Fig. 5) and a third semiconductor (71 Ikeda [68] and Fig. 5) having one end connected to a reference voltage line (L4 Ikeda [0049] and Fig. 3) and another end connected to the second semiconductor (Drains of SST and IST connected Ikeda [0087] and Fig. 3, and drain of SST is semiconductor layer 75 Ikeda [0070] and Fig. 5), wherein the third semiconductor is connected to the second storage electrode and the first gate electrode of the driving transistor through the driving gate electrode connecting member (Ikeda [0058] and [0087] and annotated Fig. 3).
Regarding Claim 17 – Ikeda modified by Kim and Na discloses all the limitations of claim 13.
The combination of Ikeda, Kim, and Na further discloses a fourth transistor (RST Ikeda [0044] and Fig. 3) including a fourth gate electrode (L5 Ikeda [0051] and Fig. 3), and a fourth semiconductor (79 Ikeda [0071] and Fig. 4) having one end connected to an initialization voltage line (L3 Ikeda [0051] and Fig. 3) and another end connected to the first storage electrode of the storage capacitor (23 Ikeda [0051] and Fig. 3).
Regarding Claim 18 – Ikeda modified by Kim and Na discloses all the limitations of claim 17.
The combination of Ikeda, Kim, and Na further discloses the initialization voltage line (passed through RST to 23 Ikeda [0051] and Fig. 3) is an initialization voltage line for a green pixel or an initialization voltage line for a red or blue pixel (Pixels 49R, 49Ga, 49Gb, or 49B Ikeda [0041] and Fig. 2).
Regarding Claim 19 – Ikeda modified by Kim and Na discloses all the limitations of claim 13.
The combination of Ikeda, Kim, and Na further discloses a fifth transistor (BCT Ikeda [0044] and Fig. 3) including a fifth gate electrode (66 Ikeda [0067] and Fig. 5) and a fifth semiconductor (65 Ikeda [0067] and Fig. 5) having one end connected to a driving voltage line (L1 Ikeda [0045] and Fig. 3) and another end connected to the first semiconductor (65 connected to 61 Ikeda [0066]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al (US 20210249394 A1, hereinafter “Ikeda”), in view of Kim et al (US 20190206971 A1, hereinafter “Kim”), and further in view of Na et al (US 20200168147 A1, hereinafter “Na”), and further in view of Choi et al (US 20220208924 A1, hereinafter “Choi”).
Regarding Claim 20 – Ikeda modified by Kim and Na discloses all the limitations of claim 19.
The combination of Ikeda, Kim, and Na fails to disclose the shielding member extends from the fifth semiconductor, and the shielding member is applied with a driving voltage.
However, Choi discloses the shielding member (SHL Choi [0180] and Fig. 17) extends from the fifth semiconductor (operation control semiconductor layer A5 through 1620 Choi [0192] and Figs. 8, 12, and 13), and the shielding member is applied with a driving voltage (ELVDD by way of PL Choi [0192] and Fig. 6).
Choi discloses a similar display circuit to Ikeda. Choi teaches connecting a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality (Choi [0257]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Choi and Ikeda to connect a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality.
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Allowable Subject Matter
Claims 1-12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 contains the following limitation not found in the prior art known to the examiner, either alone or in combination: “...the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor are disposed between the first scan line and the driving gate electrode connecting member in a cross-sectional view.”
Claims 2-12 are allowable for their dependency on claim 1.
Closest prior art:
Ikeda (US 202120249394 A1) teaches that the first semiconductor (61 [0059] and Fig. 5) and second semiconductor (75 [0059] and Fig. 5) are between the first scan line (L7 [0059] and Fig. 5) and driving gate electrode connecting member (L9 [0058] and Fig. 5), but the first gate electrode and second gate electrode are on a coincident level with the first scan line (L7 [0059] and Fig. 5).
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Kim (US 20190206971 A1) teaches the first semiconductor (120c [0066] and Fig. 5A) and second semiconductor (130c [0075] and Fig. 5A) and the first gate electrode (122 [0065] and Fig. 5A) and second gate electrode (132 [0173] and Fig. 5A) are below the first scan line (173 [0074] and Fig. 5A), but not above the driving gate electrode connecting member (130 [0070] and Fig. 5A).
Lim (US 20180047799 A1) teaches there are no conductive layers below the semiconductor layer for the transistor active regions (e.g. ACT7, Lim [0132] and Fig. 8).
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Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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