DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 19 November 2025 is acknowledged.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 25 July 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al (US 20210249394 A1, hereinafter “Ikeda”), in view of Kim et al (US 20190206971 A1, hereinafter “Kim”).
Regarding Claim 1 – Ikeda discloses a light emitting display device, comprising: a driving transistor (DRT [0065] and Fig. 3) including a first gate electrode (64 [0065] and Fig. 5) and a first semiconductor (61 [0065] and Fig. 5); a second transistor (SST [0070] and Fig. 3) including a second gate electrode (78 [0070] and Fig. 5), and a second semiconductor (75 [0070] and Fig. 5) having one end connected to a data line (L2 [0050] and Fig. 3) and another end connected to the first gate electrode of the driving transistor (DRT gate coupled to drain of SST [0047] and Fig. 3); a light emitting diode including an anode (3 including 23t [0046] and Fig. 5); a storage capacitor (Cs1 [0044] and Fig. 3) including a first storage electrode (61a [0066] and Fig. 5) connected to the anode of the light emitting diode (same node as drain of reset transistor RST [0052] and Fig. 3; 61a connected to 23t via 62, 24, and 23 in Fig. 5) and a second storage electrode (64 [0066] and Fig. 5) overlapping the first storage electrode in a plan view (61a overlapping 64 in Fig. 4); a first scan line (L7 [0036] and Fig. 3) connected to the second gate electrode of the second transistor (Gate of SST [0050] and Fig. 3); and a driving gate electrode connecting member (L9 [0058] and Figs. 4 and 5) connecting the second semiconductor of the second transistor, the second storage electrode, and the first gate electrode of the driving transistor (Figs. 4 and 5), wherein the first scan line and the driving gate electrode connecting member cross and overlap in a plan view (Cross in annotated Fig. 4), and the driving gate electrode connecting member are positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor (L9 in a different layer from 61, 75, 64, an 78 [0060] and Fig. 5).
Ikeda fails to disclose the first scan line is positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor.
However, Kim discloses the first scan line (173 Kim [0074] and Fig. 5A) is positioned on a different layer from the first gate electrode (122 Kim [0065] and Fig. 5A), the second gate electrode (132 [0074] and Fig. 5A), the first semiconductor (120c Kim [0064] and Fig. 5A), and the second semiconductor (130c Kim [0070] and Fig. 5A).
Kim discloses a display circuit analogous to Ikeda. Kim teaches the scan (gate) line may be in a different layer than the gate electrodes, which is a case of simple substitution of one existing conductive layer for another to provide a circuit path for the scan line, and the conductive layers are all known to carry electrical signals. This simple substitution of one conductive layer for another presents a prima facie case of obviousness. See MPEP 2143(I)(B). Therefore, it would have been obvious prior to the effective filing date to consider combining the teachings of Ikeda and Kim to use a simple substitution of a different conductive layer than the gate electrode and semiconductor layers for the scan line because any of the conductive layers can carry electrical signals.
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Regarding Claim 2 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim does not explicitly disclose the first scan line and the driving gate electrode connecting member cross and overlap in a plan view to configure a boost capacitor.
However, the crossing of the first scan line (L7) and driving gate electrode connecting member (L9) inherently creates a capacitor due to the existence of only dielectric layers 91 and 92 between the two lines at the location of the overlap in plan view (Overlap of L7 and L9 is shown in Ikeda Fig. 4 and intervening layers between L7 and L9 are shown in Fig. 5), and such a capacitor can be referred to as a boost capacitor. Such a boost capacitor is an inherent feature of the crossing of the scan line and driving gate electrode connecting member. See MPEP 2112(II and III). Therefore, the boost capacitor would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention.
Regarding Claim 3 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses a hold capacitor (Cs2 Ikeda [0044] and Fig. 3) including a first electrode (L1 Ikeda [0046] and Fig. 3) and a second electrode (23 Ikeda [0046] and Fig. 3), wherein the second electrode of the hold capacitor is integral with the first storage electrode (electrically connected through 62 and 24 as in Ikeda Fig. 5), and the first electrode of the hold capacitor and the first storage electrode overlap in a plan view to configure the hold capacitor (Overlap can be seen in Ikeda Fig. 5).
Regarding Claim 4 – Ikeda modified by Kim discloses all the limitations of claim 3.
The combination of Ikeda and Kim further discloses the first electrode of the hold capacitor is connected to a driving voltage line or a reference voltage line (Power supply line L1 Ikeda [0074] and Fig. 3).
Regarding Claim 5 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses a third transistor (IST Ikeda [044] and Fig. 3) including a third gate electrode (L8 Ikeda [0068] and Fig. 5) and a third semiconductor (71 Ikeda [68] and Fig. 5) having one end connected to a reference voltage line (L4 Ikeda [0049] and Fig. 3) and another end connected to the second semiconductor (Drains of SST and IST connected Ikeda [0087] and Fig. 3, and drain of SST is semiconductor layer 75 Ikeda [0070] and Fig. 5), wherein the third semiconductor is connected to the second storage electrode and the first gate electrode of the driving transistor through the driving gate electrode connecting member (Ikeda [0058] and [0087] and annotated Fig. 3).
Regarding Claim 6 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses a fourth transistor (RST Ikeda [0044] and Fig. 3) including a fourth gate electrode (L5 Ikeda [0051] and Fig. 3) and a fourth semiconductor (79 Ikeda [0071] and Fig. 4) having one end connected to an initialization voltage line (L3 Ikeda [0051] and Fig. 3) and another end connected to the first storage electrode of the storage capacitor (23 Ikeda [0051] and Fig. 3).
Regarding Claim 7 – Ikeda modified by Kim discloses all the limitations of claim 6.
The combination of Ikeda and Kim further discloses the initialization voltage line (passed through RST to 23 Ikeda [0051] and Fig. 3) is an initialization voltage line for a green pixel or an initialization voltage line for a red or blue pixel (Pixels 49R, 49Ga, 49Gb, or 49B Ikeda [0041] and Fig. 2).
Regarding Claim 8 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses a fifth transistor (BCT Ikeda [0044] and Fig. 3) including a fifth gate electrode (66 Ikeda [0067] and Fig. 5) and a fifth semiconductor (65 Ikeda [0067] and Fig. 5) having one end connected to a driving voltage line (L1 Ikeda [0045] and Fig. 3) and another end connected to the first semiconductor (65 connected to 61 Ikeda [0066]).
Regarding Claim 10 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses the first semiconductor of the driving transistor is integrally formed with the first storage electrode (both 61a Ikeda [0066] and Fig. 5).
Regarding Claim 11 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses a first conductive layer including the first scan line and the second storage electrode is positioned on a substrate (Conductive layer containing 78 and 64 on 21, Fig. 5), a first insulating film is positioned on the first conductive layer (91 Ikeda [0066] and Fig. 5), a semiconductor layer that includes the first semiconductor (61 in Ikeda Fig. 5), the second semiconductor (75 in Ikeda Fig. 5), and the first storage electrode (61a in Ikeda Fig. 5) and is formed of an oxide semiconductor ([0063]), is positioned on the first insulating film (as stated in Ikeda [0066] and shown in Fig. 5), a second insulating film is positioned on the semiconductor layer (92 Ikeda [0079] and Fig. 5), a second conductive layer is positioned on the second insulating film (the signal lines and power supply lines Ikeda [0079], for example 62, 67, 72, 73, and 77 in Fig. 5), a third insulating film is positioned on the second conductive layer (93 Ikeda [0079] and Fig. 5), and a third conductive layer is positioned on the third insulating film (an anode coupling electrode 24 and shield electrode 26, Ikeda [0079] and Fig. 5).
The combination of Ikeda and Kim fails to expressly disclose the first gate electrode and the second gate electrode are included in the second conductive layer and the data line and the driving gate electrode connecting member are included in the third conductive layer.
However, Kim discloses related art (Kim [0004-0006]) that discloses the first gate electrode (DG Kim annotated Fig. 1) and the second gate electrode (SG Kim annotated Fig. 1) are included in the second conductive layer (C2 Kim annotated Fig. 1) and the driving gate electrode connecting member (DGECM Kim annotated Fig. 1) is included in the third conductive layer (C3 Kim annotated Fig. 1).
Kim’s related art is analogous to Ikeda by disclosing a display pixel driving circuit. Kim’s related art teaches the two transistors (Tdr and Tsw, Kim [0006] and Fig. 1) connected to the driving gate electrode connecting member (DGECM in annotated Fig. 1) have gates in the second conductive layer for the benefit of direct connection the third conductive layer (C3 in annotated Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Ikeda and Kim’s related art to design the gates of the driving and switching transistors in the second conductive layer for the benefit of direct connection the third conductive layer.
The combination of Ikeda and Kim fails to disclose the data line is included in the third conductive layer.
However, the combination of Ikeda and Kim disclose multiple configurations of all three conductive layers to form the necessary connections in the same fundamental pixel drive circuit. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date that the data line can be designed in any of the three conductive layers as substitutional equivalents known for the same purpose. See MPEP 2144.06(II).
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Regarding Claim 12 – Ikeda modified by Kim discloses all the limitations of claim 1.
The combination of Ikeda and Kim further discloses the first gate electrode (122 Kim [0065] and Fig. 5A) does not overlap the first storage electrode (108 and 120 Kim [0083] and Fig. 5A) and the second storage electrode (130 Kim [0106] and Fig. 5A) in a plan view (No overlap in Figs. 4 and 5A).
Kim discloses an analogous display device to Ikeda. Kim teaches the first gate electrode does not overlap the first storage electrode to enable via connection to the gate electrode, since the gate electrode (122) and the storage capacitor electrodes (108, 120, and 130) are on different layers and layer 130 connects the gate electrode to other circuit features (Kim [0071] and Fig. 5A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to not overlap the first gate electrode and the storage electrodes to enable the use of a via to connect to the first gate electrode.
Regarding Claim 13 – Ikeda discloses a light emitting display device, comprising: a driving transistor (DRT [0065] and Fig. 3) including a first gate electrode (64 [0065] and Fig. 5) and a first semiconductor (61 [0065] and Fig. 5); a second transistor (SST [0070] and Fig. 3) including a second gate electrode (78 [0070] and Fig. 5), and a second semiconductor (75 [0070] and Fig. 5) having one end connected to a data line (L2 [0050] and Fig. 3) and another end connected to the first gate electrode of the driving transistor (DRT gate coupled to drain of SST [0047] and Fig. 3); a light emitting diode including an anode (3 including 23t [0046] and Fig. 5); and a storage capacitor including a first storage electrode (61a [0066] and Fig. 5) connected to the anode of the light emitting diode (61a connected to 23t via 62, 24, and 23 in Fig. 5) and a second storage electrode (64 [0066] and Fig. 5) overlapping the first storage electrode in a plan view (61a overlapping 64 in Fig. 4).
Ikeda fails to disclose the first gate electrode does not overlap the first storage electrode or the second storage electrode in a plan view.
However, Kim discloses the first gate electrode (122 Kim [0065] and Fig. 5A) does not overlap the first storage electrode (108 and 120 Kim [0083] and Fig. 5A) or the second storage electrode (130 Kim [0106] and Fig. 5A) in a plan view (No overlap in Figs. 4 and 5A).
Kim discloses an analogous display device to Ikeda. Kim teaches the first gate electrode does not overlap the first storage electrode to enable via connection to the gate electrode, since the gate electrode (122) and the storage capacitor electrodes (108, 120, and 130) are on different layers and layer 130 connects the gate electrode to other circuit features (Kim [0071] and Fig. 5A). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to not overlap the first gate electrode and the storage electrodes to enable the use of a via to connect to the first gate electrode.
Regarding Claim 14 – Ikeda modified by Kim discloses all the limitations of claim 13.
The combination of Ikeda and Kim further discloses a hold capacitor (Cs2 Ikeda [0044] and Fig. 3) including a first electrode (L1 Ikeda [0046] and Fig. 3) and a second electrode (23 Ikeda [0046] and Fig. 3), wherein the second electrode of the hold capacitor is integral with the first storage electrode (electrically connected through 62 and 24 as in Ikeda Fig. 5), the first electrode of the hold capacitor and the second storage electrode overlap in a plan view (Overlap can be seen in Ikeda Fig. 5), the first gate electrode does not overlap the first electrode of the hold capacitor in a plan view (122 does not overlap 108, 120, or 130 in Kim Figs. 4 and 5), and the first electrode of the hold capacitor is connected to a driving voltage line or a reference voltage line (L1 Ikeda [0055] and Fig. 3).
Regarding Claim 15 – Ikeda modified by Kim discloses all the limitations of claim 13.
The combination of Ikeda and Kim further discloses a first scan line (L7 Ikeda [0036] and Fig. 3) connected to the second gate electrode of the second transistor (Gate of SST Ikeda [0050] and Fig. 3); and a driving gate electrode connecting member (L9 Ikeda [0058] and Figs. 4 and 5) connecting the second semiconductor of the second transistor, the second storage electrode, and the first gate electrode of the driving transistor (Ikeda Figs. 4 and 5), wherein the first scan line and the driving gate electrode connecting member cross and overlap in a plan view (Cross in annotated Ikeda Fig. 4), and the driving gate electrode connecting member are positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor (L9 in a different layer from 61, 75, 64, an 78 Ikeda [0060] and Fig. 5).
Ikeda fails to disclose the first scan line is positioned on a different layer from the first gate electrode, the second gate electrode, the first semiconductor, and the second semiconductor.
However, Kim discloses the first scan line (173 Kim [0074] and Fig. 5A) is positioned on a different layer from the first gate electrode (122 Kim[0065] and Fig. 5A), the second gate electrode (132 Kim [0074] and Fig. 5A), the first semiconductor (120c Kim [0064] and Fig. 5A), and the second semiconductor (130c Kim [0070] and Fig. 5A).
Kim discloses a display circuit analogous to Ikeda. Kim teaches the scan (gate) line may be in a different layer than the gate electrodes, which is a case of simple substitution of one existing conductive layer for another to provide a circuit path for the scan line, and the conductive layers are all known to carry electrical signals. This simple substitution of one conductive layer for another presents a prima facie case of obviousness. See MPEP 2143(I)(B). Therefore, it would have been obvious prior to the effective filing date to consider combining the teachings of Ikeda and Kim to use a simple substitution of a different conductive layer than the gate electrode and semiconductor layers for the scan line because any of the conductive layers can carry electrical signals.
Regarding Claim 16 – Ikeda modified by Kim discloses all the limitations of claim 15.
The combination of Ikeda and Kim further discloses a third transistor (IST Ikeda [044] and Fig. 3) including a third gate electrode (L8 Ikeda [0068] and Fig. 5) and a third semiconductor (71 Ikeda [68] and Fig. 5) having one end connected to a reference voltage line (L4 Ikeda [0049] and Fig. 3) and another end connected to the second semiconductor (Drains of SST and IST connected Ikeda [0087] and Fig. 3, and drain of SST is semiconductor layer 75 Ikeda [0070] and Fig. 5), wherein the third semiconductor is connected to the second storage electrode and the first gate electrode of the driving transistor through the driving gate electrode connecting member (Ikeda [0058] and [0087] and annotated Fig. 3).
Regarding Claim 17 – Ikeda modified by Kim discloses all the limitations of claim 13.
The combination of Ikeda and Kim further discloses a fourth transistor (RST Ikeda [0044] and Fig. 3) including a fourth gate electrode (L5 Ikeda [0051] and Fig. 3), and a fourth semiconductor (79 Ikeda [0071] and Fig. 4) having one end connected to an initialization voltage line (L3 Ikeda [0051] and Fig. 3) and another end connected to the first storage electrode of the storage capacitor (23 Ikeda [0051] and Fig. 3).
Regarding Claim 18 – Ikeda modified by Kim discloses all the limitations of claim 17.
The combination of Ikeda and Kim further discloses the initialization voltage line (passed through RST to 23 Ikeda [0051] and Fig. 3) is an initialization voltage line for a green pixel or an initialization voltage line for a red or blue pixel (Pixels 49R, 49Ga, 49Gb, or 49B Ikeda [0041] and Fig. 2).
Regarding Claim 19 – Ikeda modified by Kim discloses all the limitations of claim 13.
The combination of Ikeda and Kim further discloses a fifth transistor (BCT Ikeda [0044] and Fig. 3) including a fifth gate electrode (66 Ikeda [0067] and Fig. 5) and a fifth semiconductor (65 Ikeda [0067] and Fig. 5) having one end connected to a driving voltage line (L1 Ikeda [0045] and Fig. 3) and another end connected to the first semiconductor (65 connected to 61 Ikeda [0066]).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda et al (US 20210249394 A1, hereinafter “Ikeda”), in view of Kim et al (US 20190206971 A1, hereinafter “Kim”), and further in view of Choi et al (US 20220208924 A1, hereinafter “Choi”).
Regarding Claim 9 – Ikeda modified by Kim discloses all the limitations of claim 8.
The combination of Ikeda and Kim fails to disclose a shielding member extending from the fifth semiconductor and overlapping the data line, wherein the shielding member is applied with a driving voltage.
However, Choi discloses a shielding member (SHL Choi [0180] and Fig. 17) extending from the fifth semiconductor (operation control semiconductor layer A5 through 1620 Choi [0192] and Figs. 8, 12, and 13) and overlapping the data line (Overlaps DL Choi [0246] and Fig. 17), wherein the shielding member is applied with a driving voltage (ELVDD by way of PL Choi [0192] and Fig. 6).
Choi discloses a similar display circuit to Ikeda. Choi teaches connecting a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality (Choi [0257]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Choi and Ikeda to connect a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality.
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Regarding Claim 20 – Ikeda modified by Kim discloses all the limitations of claim 19.
The combination of Ikeda and Kim fails to disclose a shielding member extending from the fifth semiconductor and overlapping the data line, wherein the shielding member is applied with a driving voltage.
However, Choi discloses a shielding member (SHL Choi [0180] and Fig. 17) extending from the fifth semiconductor (operation control semiconductor layer A5 through 1620 Choi [0192] and Figs. 8, 12, and 13) and overlapping the data line (Overlaps DL Choi [0246] and Fig. 17), wherein the shielding member is applied with a driving voltage (ELVDD by way of PL Choi [0192] and Fig. 6).
Choi discloses a similar display circuit to Ikeda. Choi teaches connecting a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality (Choi [0257]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Choi and Ikeda to connect a shielding member to a driving voltage and the fifth semiconductor for the benefit of improved display quality.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898