DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, species B, in the reply filed on 3/20/2026 is acknowledged. The traversal is on the ground(s) that – for the inventions – invention I cannot be made by another process than that claimed in invention II, and that the Office “will necessarily have to search the method of claim 11 while searching the structure of claim 1, and – for the species – claim 1 is generic and so a species restriction is improper.
This is not found persuasive.
"Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment." Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004). Applicant appears to argue that a tunnel junction should be understood to always have a particular crystallinity (remarks, p. 7). Though the specification may contemplate an embodiment, it is improper to import narrowing limitations from the specification into the claims when the claim language does not require it. Therefore, invention I may be made by a method different from that found in claim 11. See the restriction requirement mailed 1/27/2026. Furthermore, inventions I and II have different classifications (see restriction mailed 1/27/2026) and so require different fields of search (remarks, p. 7).
For the species, it appears that Applicant’s position is that the presence of a generic claim precludes proper species restriction (remarks, p. 8). The scope of a claim may be limited to a single disclosed embodiment (i.e., a single species, and thus be designated a specific species claim), or claim may encompass two or more of the disclosed embodiments (and thus be designated a generic or genus claim). See MPEP 806.04(e). Therefore, a species restriction is not precluded by the presence of a generic claim as multiple species may be encompassed by a generic claim.
For claim 20, Applicant’s recognition of claim 20 as appropriately belonging to invention I (remarks, p. 8) is persuasive; claim 20 is no longer withdrawn and will be considered part of the invention I grouping.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the one or more buffer layers as found in claim 7, and more than one intermediary semiconductor layer as recited in the alternative in claim 8, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Furthermore, Applicant characterizes Figure 1 as a “known layered structure” (instant specification; ¶57). Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Rejection 1/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 8-10, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kondo et al. (US 2021/0305771).
(Re Claim 1) Kondo teaches a layered structure comprising:
a substrate (85+86+87+88; view Fig. 7B upside down) comprising a p-type semiconductor material (layer 85 is a p-type semiconductor material; ¶143);
a plurality of semiconductor layers (81+83; Fig. 7B), on the substrate, comprising at least one p-on-n junction (81 is p-type and 83 is n-type; view Fig. 7B upside down; ¶¶138, 141); and a tunnel junction layer (84; Fig. 7B, ¶142) between the substrate and the plurality of semiconductor layers (Fig. 7B).
(Re Claim 2) Kondo teaches the layered structure of claim 1, wherein the tunnel junction layer comprises an n-on-p tunnel junction (n-type 84a is on p-type 85b; view Fig. 7B upside down; ¶142).
(Re Claim 3) Kondo teaches the layered structure of claim 2, wherein an n-type semiconductor tunnel layer of the n-on-p tunnel junction comprises a diffusion layer (84a; contains high-concentration n-type impurities; Fig. 7B, ¶142) formed by diffusion from the plurality of semiconductor layers to the tunnel junction layer.
Claim 3 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed diffusion layer need not be formed by the process of diffusion from the plurality of semiconductor layers to the tunnel junction layer. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
(Re Claim 6) Kondo teaches the layered structure of claim 1, wherein:
the tunnel junction layer comprises a first material (GaAs; ¶142), and the substrate comprises the first material (layer 85 comprises GaAs with Al content at 0; ¶143).
(Re Claim 8) Kondo teaches the layered structure of claim 1, wherein the at least one p-on-n junction comprises:
an n-type semiconductor layer (83; ¶141);
a p-type semiconductor layer (81; ¶138); and
one or more intermediary semiconductor layers (82; Fig. 7B, ¶142) between the n-type semiconductor layer and the p-type semiconductor layer, wherein the one or more intermediary semiconductor layers comprises an active layer for emitting (emitting: ¶142) or absorbing light.
(Re Claim 9) Kondo teaches the layered structure of claim 1, wherein the at least one p-on-n junction comprises an n-type reflector (n-type; ¶¶36, 141) and a p-type reflector.
(Re Claim 10) Kondo teaches the layered structure of claim 1, wherein the layered structure forms one of: a light emitting diode (LED), a vertical cavity surface emitting laser (VCSEL) (VCSEL; Fig. 7B), an edge emitting laser, and a photodetector.
(Re Claim 20) Kondo teaches the layered structure comprising:
a substrate (85+86+87+88; view Fig. 7B upside down) comprising p-type semiconductor material (layer 85 is a p-type semiconductor material; ¶143);
one or more semiconductor layers (81+83; Fig. 7B) for forming a device (VCSEL; Fig. 7B); and a tunnel junction layer (84; Fig. 7B, ¶142) between the substrate and the one or more semiconductor layers (Fig. 7B).
Rejection 2/2
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Koelle et al. (US 2005/0089074) and Dai et al. (US 2023/0307889).
(Re Claim 1) Koelle teaches a layered structure comprising:
a substrate (18; Fig. 3) comprising a p-type semiconductor material (p-type GaAs; ¶21); and
a plurality of semiconductor layers (14+16; Fig. 3), on the substrate, comprising at least one p-on-n junction (layer 14 is p-type and layer 16 is n-type; ¶39); Koelle has not been shown to explicitly teach a tunnel junction layer between the substrate and the plurality of semiconductor layers.
Dai teaches forming a lower mirror (14; Fig. 2) having a tunnel junction layer (143; Fig. 2).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the lower mirror 14 taught by Dai for the lower mirror 16 of Koelle, as Dai’s lower mirror configuration allows for reduced resistance (Dai: ¶33).
This results in modified Koelle teaching a plurality of semiconductor layers (14 from Koelle, and layers 141 of Dai; see Fig. 3 of Koelle and Fig. 2 of Dai), on the substrate, comprising at least one p-on-n junction (Koelle’s layer 14 is p-type and Dai’s layer 141 is n-type; Koelle: ¶39; Dai: ¶33); and
a tunnel junction layer (Dai: 143; Fig. 2) between the substrate and the plurality of semiconductor layers (Koelle: Fig. 3).
(Re Claim 7) Modified Koelle teaches the layered structure of claim 1, further comprising one or more buffer layers between the substrate and the tunnel junction layer (17; Fig. 3).
(Re Claim 8) Modified Koelle teaches the layered structure of claim 1, wherein the at least one p-on-n junction comprises:
an n-type semiconductor layer (Dai: 141; Fig. 2, ¶33);
a p-type semiconductor layer (Koelle: 14; ¶39); and
one or more intermediary semiconductor layers (19; Fig. 3) between the n-type semiconductor layer and the p-type semiconductor layer, wherein the one or more intermediary semiconductor layers comprises an active layer (20; Fig. 3) for emitting (emitting: ¶19) or absorbing light.
(Re Claim 9) Modified Koelle teaches the layered structure of claim 1, wherein the at least one p-on-n junction comprises an n-type reflector (Dai’s 141 as part of the mirror structure; ¶33) and a p-type reflector (Koelle: DBR mirror 16; ¶39).
(Re Claim 10) Modified Koelle teaches the layered structure of claim 1, wherein the layered structure forms one of: a light emitting diode (LED), a vertical cavity surface emitting laser (VCSEL) (Koelle: ¶39), an edge emitting laser, and a photodetector.
(Re Claim 20) Koelle teaches the layered structure comprising:
a substrate (18; Fig. 3) comprising p-type semiconductor material (p-type GaAs; ¶21); and
one or more semiconductor layers (p-type GaAs; ¶21) for forming a device (VCSEL: ¶39); Koelle has not been shown to explicitly teach a tunnel junction layer between the substrate and the one or more semiconductor layers.
Dai teaches forming a lower mirror (14; Fig. 2) having a tunnel junction layer (143; Fig. 2).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the lower mirror 14 taught by Dai for the lower mirror 16 of Koelle, as Dai’s lower mirror configuration allows for reduced resistance (Dai: ¶33).
This results in modified Koelle teaching a one or more semiconductor layers (14 from Koelle, and layers 141 of Dai; see Fig. 3 of Koelle and Fig. 2 of Dai) for forming a device (Koelle: VCSEL; ¶39; Dai: VCSEL: ¶2); and
a tunnel junction layer (Dai: 143; Fig. 2) between the substrate and the one or more semiconductor layers (Koelle: Fig. 3).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Koelle et al. (US 2005/0089074) and Dai et al. (US 2023/0307889) as applied to claim 1 above, and further in view of Kondo (US 2018/0006645) of record.
(Re Claim 2) Modified Koelle teaches the layered structure of claim 1, but has not been shown to explicitly teach the tunnel junction layer comprises an n-on-p tunnel junction.
Kondo teaches forming a tunnel junction layer (15; Fig. 14A) formed of an n-type (15a; Fig. 14A) and a p-type (15b; Fig. 14A) layer.
As Dai does not describe the particular structure of the tunnel junction layer 143, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the structure of Kondo’s tunnel junction layer (15; Fig. 14A), as Kondo’s tunnel junction layer contact orientation is suitable for providing separation between an n-type DBR that is part of a VCSEL device (Kondo: Fig. 14A; Koelle: “each of the first and second mirrors 14, 16 includes a system of alternating layers of different refractive index materials that forms a distributed Bragg reflector (DBR)” (¶21); ¶39) and another p-type layer while allowing for electrical interaction with the VCSEL device. See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686.
Doing so results in the tunnel junction layer of modified Koelle having an n-type layer on top of a p-type layer, where the p-type layer is closer to the substrate of modified Koelle, and so the tunnel junction layer comprises an n-on-p tunnel junction.
(Re Claim 3) Modified Koelle teaches the layered structure of claim 2, wherein an n-type semiconductor tunnel layer of the n-on-p tunnel junction comprises a diffusion layer (the n-type layer of Dai’s 143 in view of Kondo) formed by diffusion (15a contains n-type dopants at high concentration; Kondo: ¶68) from the plurality of semiconductor layers to the tunnel junction layer.
Claim 3 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed diffusion layer need not be formed by the process of diffusion from the plurality of semiconductor layers to the tunnel junction layer. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Koelle et al. (US 2005/0089074) and Dai et al. (US 2023/0307889) as applied to claim 1 above, and further in view of Roucka (US 2021/0305782), Li et al. (US 2021/0091244), and Kim (US 2014/0273323).
(Re Claim 4) Modified Koelle teaches the layered structure of claim 1, but has not been shown to teach the p-type semiconductor material of the substrate comprises Ge.
Roucka teaches that a substrate may be made from GaAs or Ge (¶52).
Li teaches forming a p-doped Ge substrate (78; Fig. 5, ¶34).
Furthermore, a PHOSITA would find it obvious to dope the semiconductor material comprising Ge of modified Koelle such that it is p-type, as Koelle states that the substrate 18 may be p-type (Koelle: ¶21), Ge and GaAs are art recognized alternative materials for forming VCSEL substrates (Roucka: ¶52), and p-type Ge substrates are known in the art (Li: ¶34). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004). P-type Ge substrates also provide good hole mobility and reduced resistance (Kim: ¶156).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Koelle et al. (US 2005/0089074) and Dai et al. (US 2023/0307889) as applied to claim 1 above, and further in view of Mascarenhas (US 2002/0117675) and Kim (US 2014/0273323).
(Re Claim 5) Modified Koelle teaches the layered structure of claim 1, but has not been shown to teach the tunnel junction layer comprises Ge.
Mascarenhas teaches forming a tunnel junction (31; Fig. 1) using Ge (¶38).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the Dai’s tunnel junction 143 in modified Kim using Ge, as taught by Mascarenhas, as Ge provides for high p-type concentration, increased hole mobility, and reduced resistance (Kim: ¶156).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Koelle et al. (US 2005/0089074) and Dai et al. (US 2023/0307889) as applied to claim 1 above, and further in view of Mascarenhas (US 2002/0117675), Roucka (US 2021/0305782), Li et al. (US 2021/0091244), and Kim (US 2014/0273323).
(Re Claim 6) Modified Koelle teaches the layered structure of claim 1, but has not been shown to teach the layered structure wherein:
the tunnel junction layer comprises a first material, and the substrate comprises the first material.
Mascarenhas teaches forming a tunnel junction (31; Fig. 1) using Ge (¶38).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the Dai’s tunnel junction 143 in modified Kim using Ge, as taught by Mascarenhas, as Ge provides for high p-type concentration, increased hole mobility, and reduced resistance (Kim: ¶156).
Roucka teaches that a substrate may be made from GaAs or Ge (¶52).
Li teaches forming a p-doped Ge substrate (78; Fig. 5, ¶34).
Furthermore, a PHOSITA would find it obvious to dope the semiconductor material comprising Ge of modified Koelle such that it is p-type, as Koelle states that the substrate 18 may be p-type (Koelle: ¶21), Ge and GaAs are art recognized alternative materials for forming VCSEL substrates (Roucka: ¶52), and p-type Ge substrates are known in the art (Li: ¶34). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004). P-type Ge substrates also provide good hole mobility and reduced resistance (Kim: ¶156).
Forming the tunnel junction layer and the substrate from Ge results in modified Koelle teaching the layered structure wherein: the tunnel junction layer comprises a first material (Ge from Masarenhas), and the substrate comprises the first material (from Roucka and Li).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dummer et al. (US 2020/0278426) teaches a layered structure comprising a tunnel junction (Fig. 24).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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