Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "420" and "425" have both been used to designate silicon-and-oxygen-containing material.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “420” has been used to designate both silicon-containing material and silicon-and-oxygen-containing material.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5-7 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 5 is stated to be dependent on itself, and references claim 4 without stating dependency on it. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. For the purposes of claim interpretation, claim 4 will be interpreted to be dependent on claim 4.
Claims 6 and 7 are dependent on claim 5 and thus rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mukherjee et al. (US 20170125241 A1).
Regarding claim 19, FIG. 4 and FIG. 5C of Mukherjee et al. teach a semiconductor structure (paragraph 0009) comprising:
a substrate (502; FIG. 5C; paragraph 0049);
a layer of silicon-and-carbon-containing material (402, 504; FIG. 4; FIG. 5C; paragraph 0063) overlying the substrate; and
a layer of silicon-and-oxygen-containing material (408, 506; FIG. 4; FIG. 5C; paragraph 0068) overlying the layer of silicon- and-carbon-containing material, wherein an interface (paragraph 0065) (“discontinuous”) between the layer of silicon-and-carbon-containing material and the layer of silicon-and-oxygen-containing material is free of silicon- oxygen-and-carbon-containing material (412; FIG. 4; paragraph 0068) (one side of the interface is free of carbon).
Regarding claim 20, Mukherjee et al. teaches the semiconductor structure of claim 19, wherein the layer of silicon-and- oxygen-containing material is formed by:
depositing a layer of silicon-containing material (408; FIG. 4; paragraph 0066); and
subsequent an amount of deposition of the layer of silicon-containing, oxidizing the layer of silicon-containing material (412; FIG. 4; paragraph 0068) to form the layer of silicon- and-oxygen-containing material (506; FIG. 5C; paragraph 0068).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 8, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. in view of Harada et al. (US 20230093981 A1).
Regarding Claim 1, FIG. 2, FIG. 4, and FIG. 5C of Mukherjee et al. teaches a semiconductor processing method (400; FIG. 4; paragraph 0047) comprising:
a substrate (502; FIG. 5C; paragraph 0049) housed within a processing region of a semiconductor processing chamber (200; FIG. 2; paragraph 0031), wherein the substrate comprises a layer of silicon-and- carbon-containing material (504; FIG. 5C; paragraph 0063);
providing a silicon-containing precursor (408; FIG. 4; paragraph 0066) to the processing region of the semiconductor processing chamber;
contacting the substrate with the silicon-containing precursor (408; FIG. 4; paragraph 0066), wherein the contacting deposits a layer of silicon-containing material (506; FIG. 5C; paragraph 0068) on the layer of silicon-and-carbon- containing material;
providing an oxygen-containing precursor (410; FIG. 4; paragraph 0067) to the processing region of the semiconductor processing chamber; and
contacting the substrate with the oxygen-containing precursor (412; FIG. 4; paragraph 0068), wherein the contacting oxidizes the layer of silicon-containing material to form a layer of silicon-and- oxygen-containing material (506; FIG. 5C; paragraph 0068).
Mukherjee et al. does not teach performing a pre-treatment on the substrate wherein the pre-treatment removes native oxide or residue from a surface of the layer of silicon-and-carbon-containing material.
Harada et al. teaches the oxidation of the SiN film and the O-added SiN film formed in the first cycle, which can be modified to contain carbon (paragraph 0069), effectively suppressing residual N while promoting the cleaning of the interface (paragraph 0141).
Mukherjee et al. and Harada et al. are both considered analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Mukherjee et al. so that a pre-treatment is performed on the substrate. This optimizes the interface by reducing defects at the interface and reducing leak paths (paragraph 0141).
Regarding claim 2, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. FIG. 4 of Mukherjee et al. further teaches the method further comprising forming plasma effluents (410; FIG. 4; paragraph 0067) of the silicon-containing precursor, the oxygen- containing precursor (410; FIG. 4; paragraph 0067), or both.
Regarding claim 3, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. FIG. 4 of Mukherjee et al. further teaches the plasma effluents (410; FIG. 4; paragraph 0067) of the silicon-containing precursor, the oxygen-containing precursor (410; FIG. 4; paragraph 0067), or both are formed at a plasma power of greater than or about 750 W (paragraph 0061).
Regarding claim 8, Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. FIG. 4 of Mukherjee et al. further teaches depositing the layer of silicon-containing material (408; FIG. 4; paragraph 0066) comprises a physical vapor deposition (PVD), a chemical vapor deposition (CVD), or an evaporation deposition (paragraph 0062, paragraph 0066).
Regarding claim 10, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. Mukherjee et al. further teaches the substrate wherein the oxygen- containing precursor comprises diatomic oxygen (02), ozone (03), steam (H2O), or hydrogen peroxide (H202) (paragraph 0061).
Regarding claim 11, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. FIG. 2 and FIG. 4 of Mukherjee et al. further teach the method wherein a temperature in the processing region (200; FIG. 2; paragraph 0031) is maintained at less than or about 1,200 °C (paragraph 0060) while contacting the substrate with the oxygen-containing precursor (410; FIG. 4; paragraph 0067).
Regarding claim 12, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 11. FIG. 4 of Mukherjee et al. further teaches the method wherein a pressure in the processing region is maintained at less than or about 20 Torr (paragraph 0060) while contacting the substrate with the oxygen-containing precursor (410; FIG. 4; paragraph 0067).
Claims 13, 14, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. in view of Girard et al. (US 20160111272 A1).
Regarding claim 13, FIG. 4 and FIG. 5C of Mukherjee et al. teaches a semiconductor processing method (400; FIG. 4; paragraph 0047) comprising:
a substrate (502; FIG. 5C; paragraph 0049) housed within a processing region of a semiconductor processing chamber (200; FIG. 2; paragraph 0031), wherein the substrate comprises a layer of silicon-and- carbon-containing material (504; FIG. 5C; paragraph 0063);
providing a silicon-containing precursor (408; FIG. 4; paragraph 0066) to a processing region of the semiconductor processing chamber (200; FIG. 2; paragraph 0031), wherein a substrate (502; FIG. 5C; paragraph 0049) is housed within the processing region, and wherein the substrate comprises a layer of silicon-and-carbon-containing material (504; FIG. 5C; paragraph 0063);
contacting the substrate with the silicon-containing precursor (paragraph 0066), wherein the contacting deposits a layer of silicon-containing material on the layer of silicon-and-carbon-containing material (504; FIG. 5C; paragraph 0063);
providing an oxygen-containing precursor (410; FIG. 4; paragraph 0067) to the processing region of the semiconductor processing chamber; and
contacting the substrate with the oxygen-containing precursor (412; FIG. 4; paragraph 0068), wherein the contacting oxidizes the layer of silicon-containing material to form a layer of silicon-and- oxygen-containing material (506; FIG. 5C; paragraph 0068).
Mukherjee et al. does not teach that the semiconductor processing method includes and the layer of silicon-containing material being characterized by a thickness of less than or about 400 Å.
Girard et al. teaches that ALD sequence was repeated for 200 cycles, until the deposited layer achieved suitable thickness for film characterization (i.e. over 100 Å) (paragraph 313).
Mukherjee et al. and Girard et al. are both considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Mukherjee et al. to have a layer of silicon at less than or about 400 Å. Doing so would give the silicon layer suitable thickness for film characterization (paragraph 313).
Regarding claim 14, the combination of Mukherjee et al. in view of Girard et al. teaches the semiconductor processing method of claim 13. Mukherjee et al. does not teach wherein the layer of silicon-containing material comprises amorphous silicon.
Girard et al. teaches the silicon film is an amorphous silicon film (claim 18).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use amorphous silicon. The silicon-containing film being in a liquid form would allow it to be easily forced into the semiconductor processor and vaporized to deliver the silicon to the substrate (paragraph 0263).
Regarding claim 17, the combination of Mukherjee et al. in view of Girard et al. teaches the semiconductor processing method of claim 13. Mukherjee et al. further teaches the method wherein contacting the substrate with the oxygen-containing precursor oxidizes (412; FIG. 4; paragraph 0068) only the layer of silicon-containing material (506; FIG. 5C; paragraph 0068).
Regarding claim 18, the combination of Mukherjee et al. in view of Girard et al. teaches the semiconductor processing method of claim 13. Mukherjee et al. further teaches the method wherein an interface (paragraph 0065) (“discontinuous”) between the layer of silicon-and-carbon-containing material (504; FIG. 5C; paragraph 0063) and the layer of silicon-and-oxygen-containing material (506; FIG. 5C; paragraph 0068) is free of silicon-oxygen-and-carbon-containing material (412; FIG. 4; paragraph 0068).
Claims 4, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. in view of Harada et al. and further in view of Girard et al..
Regarding claim 4, the combination of Mukherjee et al. in view of Harada et al. teaches the semiconductor processing method of claim 1. Neither Mukherjee et al. nor Harada et al. teach the pre- treatment comprising annealing the substrate in an oxygen free environment.
Girard et al. teaches performing the annealing in a H-containing atmosphere, a N-containing atmosphere, an O-containing atmosphere, or combinations thereof (paragraph 302), with the pointed mention of the oxygen atmosphere implies its potential to be absent.
Mukherjee et al., Harada et al., and Girard et al. are all considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious for a person of ordinary skill in the art would have recognized prior to the filing date of the application to anneal the substrate in an oxygen free environment. This is a known aspect of the annealing process (paragraph 0302).
Regarding claim 5, the combination of Mukherjee et al. in view of Harada et al. and further in view of Girard et al. teaches the semiconductor processing method of claim 4 as best interpreted in the 112(d) issue above. Neither Mukherjee et al. nor Harada teach the annealing is performed at a temperature greater than or about 500 °C. Girard et al. teaches the silicon-containing film may be exposed to a temperature ranging from approximately 200° C. and approximately 1000° C (paragraph 0302).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Mukherjee et al. to include the teachings of Girard et al. by performing an annealing process at 500°C or greater, as that is known to be an effective temperature range for the annealing process (paragraph 0302).
Regarding claim 9, the combination of Mukherjee et al. in view of Harada et al. and further in view of Girard et al. teaches the semiconductor processing method of claim 4. Neither Mukherjee et al. nor Harada teach wherein the layer of silicon-containing material is characterized by a thickness of less than or about 400 Å.
Girard et al. teaches that ALD sequence was repeated for 200 cycles, until the deposited layer achieved suitable thickness for film characterization (i.e. over 100 Å) (paragraph 313).
Mukherjee et al., Harada et al., and Girard et al. are all considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Mukherjee et al. to have a layer of silicon at less than or about 400 Å. Doing so would give the silicon layer suitable thickness for film characterization (paragraph 313).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. in view of Girard et al. and further in view of Harada et al..
Regarding claim 15, the combination of Mukherjee et al. in view of Girard et al. teaches the semiconductor processing method of claim 13. Neither Mukherjee et al. nor Girard et al. teach the method further comprising: providing an aluminum-containing precursor or a hafnium-containing precursor to the processing region of the semiconductor processing chamber with the oxygen-containing precursor
Harada et al. teaches a metal nitride film (such as aluminum nitride or hafnium nitride) or a metal carbonitride film (such as aluminum carbonitride and hafnium carbonitride) may be formed as the first film a metal oxide film (such as aluminum oxide and hafnium oxide) may be formed as the second film (paragraph 0151).
Mukherjee et al., Harada et al., and Girard et al. are all considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Mukherjee et al. to provide to an aluminum-containing precursor or a hafnium-containing precursor to the processing region of the semiconductor processing chamber with the oxygen-containing precursor. These are known carriers of the necessary precursors needed to form the layers (paragraph 0151).
Regarding claim 16, the combination of Harada et al. in view of Girard et al. teaches the semiconductor processing method of claim 13. Neither Mukherjee et al. nor Girard et al. teach the further teaches the method further comprising: adjusting a temperature in the processing region while contacting the substrate with the oxygen-containing precursor.
FIG. 2 of Harada et al. teaches adjusting a degree of conducting electricity of the heater (207; FIG. 2; paragraph) based on the temperature information detected by the temperature sensor (263; FIG. 2; paragraph 0035), so the temperature inside the process chamber (201; FIG. 2; paragraph 0035) becomes a desired temperature distribution, such as when adding oxygen (paragraph 0098).
Mukherjee et al., Harada et al., and Girard et al. are all considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Mukherjee et al. to allow the adjusting a temperature in the processing region while contacting the substrate with the oxygen-containing precursor. This allows the film to be oxidized properly (paragraph 0098).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee et al. in view of Harada et al. and further in view of Girard et al. and Wang et al. (US 20170148642 A1).
Regarding claim 6, the combination of Mukherjee et al. in view of Harada et al. and further in view of Girard et al. teaches the semiconductor processing method of claim 5. Mukherjee does not teach wherein the pre-treatment comprises:
providing a halogen-containing precursor to the processing region;
forming plasma effluents of the halogen-containing precursor; and
contacting the substrate with the plasma effluents of the halogen-containing precursor, wherein the contacting removes the native oxide or residue from the surface of the layer of silicon-and-carbon-containing material.
Harada et al. teaches the oxidation of the SiN film and the O-added SiN film formed in the first cycle, which can be modified to contain carbon (paragraph 0069), effectively suppressing residual N while promoting the cleaning of the interface (paragraph 0141). Harada et al. does not teach:
providing a halogen-containing precursor to the processing region;
forming plasma effluents of the halogen-containing precursor; and
contacting the substrate with the plasma effluents of the halogen-containing precursor, wherein the contacting removes the native oxide or residue from the surface of the layer of silicon-and-carbon-containing material.
Wang et al. teaches a fluorine-containing precursor (or plasma effluents formed in a remote plasma from plasma effluents formed from a fluorine-containing precursor) may be flowed into the substrate processing region to etch the substrate (paragraph 0031).
Mukherjee et al., Harada et al., Girard et al., and Wang et al. are both considered to be analogous to the claimed invention because they are in the same field of laying materials onto semiconductor substrates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date to modify Mukherjee et al. to perform the pre-treatment process with a halogen-containing precursor and remove the native oxide or residue from the surface of the layer of silicon-and-carbon-containing material. This optimizes the interface by reducing defects at the interface and reducing leak paths (Harada et al., paragraph 0141) with halogens being known to be used in dry etch process with the ability to gently remove material from miniature structures with minimal physical disturbance (Wang et al., paragraph 0004).
Regarding claim 7, the combination of Mukherjee et al. in view of Harada et al. and further in view of Girard et al. and Wang et al. teach the semiconductor processing method of claim 6. Mukherjee et al., Harada et al., and Girard et al. do not teach the method wherein the halogen- containing precursor comprises a fluorine-containing precursor
Wang et al. teaches a fluorine-containing precursor (or plasma effluents formed in a remote plasma from plasma effluents formed from a fluorine-containing precursor) may be flowed into the substrate processing region to etch the substrate (paragraph 0031).
It would be obvious to a person of ordinary skill in the art before the effective filing date to modify Mukherjee et al. to use a fluorine-containing precursor for pre-treatment. Fluorine is a halogen known to be used in dry etch process with the ability to gently remove material from miniature structures with minimal physical disturbance (paragraph 0004).
Response to Arguments
In response to applicant's argument that the references do not address issues associated with silicon-oxygen-and-carbon material being formed at the interface between a layer of silicon-containing material and a layer of silicon-and-carbon-containing material in claims 1, 13, and 19, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant’s other arguments with respect to claims 1, 13 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheng et al. (20180114834 A1) concerns forming semiconductor device containing structures with nanosheet transistors. Chen et al. (US 20200013632 A1) concerns methods of etching a substrate processing region in a semiconductor processing chamber.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00am- 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights