DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3,11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2014/0209922 A1 to Ota et al., “Ota”.
Regarding claim 1, Ota discloses a high electron mobility transistor (FIG. 23), comprising:
a semiconductor channel layer (“CH” ¶ [0065]-[0068]) and a semiconductor barrier layer (“ES” ¶ [0067]-[0068]), disposed on a substrate (“SUB” ¶ [0062]) in sequence;
a source electrode (“SE” ¶ [0069]) and a drain electrode (“DE” ¶ [0069]), disposed on the semiconductor channel layer (“CH”);
a semiconductor cap layer (“CAP” ¶ [0070]), disposed on the semiconductor barrier layer (“ES”);
a first dielectric layer (“IL1” [0238]), disposed over the source electrode (“SE”), the semiconductor cap layer (“CAP”) and the drain electrode (“DE”);
a first via (“P1”, ¶ [0239]), passing through the first dielectric layer (“IL1”) and extended downward onto (onto but not directly contacting) the semiconductor cap layer (“CAP”);
a gate electrode (“M1”, analogous to Applicant’s gate electrode 129), disposed on the first dielectric layer (“IL1”) and in contact with the first via (“P1”);
a first field plate (lower right-side portion of “GE2”, see Examiner-annotated figure below), disposed in the first dielectric layer (“IL1”); and
a second field plate (one of the left portions of “GE2”, see Examiner-annotated figure below), disposed on (“on” = contacting) the first dielectric layer (“IL1”) and in (physical and electrical) contact with the first field plate.
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Regarding claim 3, Ota discloses the high electron mobility transistor (FIG. 23) of claim 1, and Ota further discloses (see Examiner-annotated figure above) wherein an angle (between dashed-arrow lines) between a sidewall and a bottom surface of the first field plate (“GE2”) is greater than 90 degrees (as pictured, due to tapered sidewall of “CAP” and “IF”).
Regarding claim 11, Ota discloses the high electron mobility transistor (FIG. 23) of claim 1, and Ota further discloses a dielectric segment (portion of “IF”), located between and laterally separated from the semiconductor cap layer (“CAP”) and the drain electrode (“DE”);
a third field plate (portion of “GE2” to the left of the second field plate, see Examiner-annotated figure below), abutting a side of the dielectric segment (segment of “IF”); and
a fourth field plate (portion of “GE2” to the left of the third field plate, see Examiner-annotated figure below), disposed on a top surface of the dielectric segment (“IF”), wherein the third field plate and the fourth field plate are connected to each other and extended continuously from the side of the dielectric segment (“IF”) onto the top surface of the dielectric segment.
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Claims 1,4-6,10 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by U.S. Patent Application Publication Number 2023/0080636 A1 to Macelwee, “Macelwee”.
Regarding claim 1, Macelwee discloses a high electron mobility transistor (Fig. 1, Fig. 2, ¶ [0020]), comprising:
a semiconductor channel layer (GaN 106) and a semiconductor barrier layer (AlGaN 108), disposed on a substrate (silicon 102) in sequence;
a source electrode (arrow labeled “Source” including 122) and a drain electrode (arrow labeled “Drain” including 124), disposed on the semiconductor channel layer (106);
a semiconductor cap layer (p-GaN 126), disposed on the semiconductor barrier layer (108);
a first dielectric layer (141), disposed over the source electrode (122), the semiconductor cap layer (126) and the drain electrode (124);
a first via (128), passing through the first dielectric layer (141) and extended downward onto the semiconductor cap layer (126);
a gate electrode (“Contact” and/or M1 above 128, analogous to Applicant’s gate electrode 129), disposed (indirectly) on the first dielectric layer (141) and in (physical and/or electrical) contact with the first via (128);
a first field plate (e.g. 130), disposed in the first dielectric layer (141); and
a second field plate (e.g. 142), disposed (directly) on the first dielectric layer and in (electrical) contact with the first field plate (130).
Regarding claim 4, Macelwee discloses (Fig. 1, ¶ [0020]) the high electron mobility transistor of claim 1, and Macelwee further discloses:
a second dielectric layer (121), disposed on the source electrode (122), the semiconductor cap layer (126) and the drain electrode (124), and located below the first dielectric layer (141); and
an etch stop layer (131, formed of silicon nitride with is an etch stop material, ¶ [0020]), disposed on the second dielectric layer (121), wherein a bottom surface of the first field plate (130) is in contact with the etch stop layer (131).
Regarding claim 5, Macelwee discloses (Fig. 1, ¶ [0020]) the high electron mobility transistor of claim 4, and Macelwee further discloses wherein the first via (filled with 128) further passes through the etch stop layer (131) and the second dielectric layer (121).
Regarding claim 6, Macelwee discloses (Fig. 1, ¶ [0020]) the high electron mobility transistor of claim 4, and Macelwee further discloses a second via (filled with “Contact” above source 122), passing through the first dielectric layer (141), the etch stop layer (131) and the second dielectric layer (121), and extending downward onto the source electrode (122);
a first wire (e.g. wire M1 of source metal 152), disposed (indirectly) on the first dielectric layer (141) and in contact with the second via (filled with “Contact” above source 122);
a third via (filled with “Contact” above drain 124, zoomed in with Fig. 2), passing through the first dielectric layer (141), the etch stop layer (131) and the second dielectric layer (121), and extending downward onto the drain electrode (124); and
a second wire (e.g. wire M1 of drain metal 154), disposed (indirectly) on the first dielectric layer (141) and in contact with the third via.
Regarding claim 10, Macelwee discloses (Fig. 1, ¶ [0020]) the high electron mobility transistor of claim 1, and Macelwee further discloses a third dielectric layer (151) disposed (indirectly) on the semiconductor barrier layer (108), wherein both a portion (portion 152) of the source electrode (arrow labeled “Source”) and a portion (154) of the drain electrode (arrow labeled “Drain”) are extended onto a top surface (as pictured) of the third dielectric layer (151).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2022/0393024 A1 to Hao et al., “Hao”, in view of U.S. Patent Application Publication Number 2020/0365718 A1 to Lee et al. “Lee”.
Regarding claim 1, Hao discloses a high electron mobility transistor (e.g. FIG. 1), comprising:
a semiconductor channel layer (106, ¶ [0024],[0025]) and a semiconductor barrier layer (108, ¶ [0024],[0025]), disposed on a substrate (102, ¶ [0022]) in sequence;
a source electrode (110, ¶ [0026]) and a drain electrode (112, ¶ [0026]), disposed on the semiconductor channel layer (106);
a semiconductor cap layer (116, ¶ [0027],[0028]) disposed on the semiconductor barrier layer;
a first dielectric layer (120, ¶ [0032]), disposed over the source electrode (110), the semiconductor cap layer (116) and the drain electrode (112);
a gate electrode (118, ¶ [0027]-[0028]), disposed on (“on” = contacting) the first dielectric layer;
a first field plate (e.g. portion P2, ¶ [0041]), disposed in the first dielectric layer (120); and
a second field plate (e.g. portion P6, ¶ [0041]), disposed on (“on” = contacting) the first dielectric layer (120) and in (electrical) contact with the first field plate (P2).
Hao fails to clearly teach a first via, passing through the first dielectric layer (120) and extending downward onto the semiconductor cap layer (116), and the gate electrode in contact with the first via.
Lee teaches (FIG. 2H) a first via (portion of 124 in recess 118, ¶ [0023],[0049]) passing through a first dielectric layer (e.g. 110, ¶ [0032]) and extending downward onto a semiconductor cap layer (109, ¶ [0037]-[0039]), and a gate electrode (e.g. 140, ¶ [0050], analogous to Applicant’s gate electrode 129) in contact with the first via (124).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Hao with a first via connecting the field plates to the gate as taught by Lee since a gate connected field plate can reduce the electric field intensity at the side of the gate near the drain thereby improving breakdown voltage and allowing the device to be used in high-voltage operating environments (Lee ¶ [0003],[0012],[0034]).
Regarding claim 2, Hao in view of Lee yields the high electron mobility transistor of claim 1, and Hao in view of Lee further yields wherein the first via (via 124 from Lee as applied to the metal layer FIG. 3G of Hao), the gate electrode (140 from Lee as applied to the metal layer FIG. 3G of Hao), the first field plate (Hao P2) and the second field plate (Hao P6) are all constructed of a first metal layer (Hao FIG. 3G layer 130’, ¶ [0055],[0034],[0035]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2014/0209922 A1 to Ota et al., “Ota”, in view of U.S. Patent Application Publication Number 2022/0157977 A1 to Lei et al., “Lei”.
Regarding claim 12, although Ota discloses the high electron mobility transistor (FIG. 23) of claim 11, and Ota further teaches (e.g. FIG. 5) wherein the source electrode (“SE”) and the drain electrode (“DE”) are constructed from a single metal layer (MF1) and teaches (FIG. 23) wherein the third field plate (portion of GE2, see Examiner-annotated figure above) and the fourth field plate (portion of “GE2”, see Examiner-annotated figure above) are constructed of a single metal layer, Ota fails to clearly anticipate wherein the source electrode, the drain electrode, the third field plate, and the fourth field plate are all constructed of a second metal layer.
Lei teaches (FIG. 3A) forming a source electrode (“S” 140, ¶ [0041]), a drain electrode (“D” 142, ¶ [0041]), a third field plate (FIG. 2F portion of 232, ¶ [0040]) and a fourth field plate (adjacent portion of 132) all constructed of a single metal layer (¶ [0042]: The process of depositing the metal into the source and drain openings may be performed concurrently with the process 200F. The process of etching the deposited metal to form the source and drain contacts 140, 142 may also be performed concurrently with the process 200F, using the same etch mask”, no “first” metal layer is claimed in claims 1 and 11, so the source/drain/field plate metal may be considered a “second” metal layer).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ota with the source, drain, third, and fourth field plates of a single metal layer as taught by Lei in order to reduce the number of manufacturing steps by forming elements simultaneously.
Allowable Subject Matter
Claims 7-9,13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2024/0063219 A1 to Sharma et al. teaches a high electron mobility transistor (e.g. FIG. 1), comprising: a semiconductor channel layer (118, ¶ [0040]-[0042]) and a semiconductor barrier layer (120, ¶ [0040]-[0042]), disposed on a substrate (114) in sequence; a source electrode (140, ¶ [0045]) and a drain electrode (142, ¶ [0045]), disposed on the semiconductor channel layer (118); a semiconductor cap layer (150, ¶ [0045]), disposed on the semiconductor barrier layer; a first dielectric layer (126, ¶ [0043]), disposed on the source electrode (140), over the semiconductor cap layer and on the drain electrode (142); a first via (filled with 152 and 154), passing through the first dielectric layer (126) and extended downward onto the semiconductor cap layer (150); a gate electrode (152 and 154), disposed on the first dielectric layer (126) and in contact with the first via; a first field plate (FIG. 6A, right portion 160 of field plate 146, ¶ [0046],[0054]), disposed in the first dielectric layer (126); and a second field plate (FIG. 6A left portion of field plate 146 to the left of bend 164, ¶ [0046]), disposed on (“on” = in contact with) the first dielectric layer (126) and in contact with the first field plate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891