DETAILED ACTION
This office action is in response to reply filed 4/24/2026.
Claims 6-9 are pending. Claims 1-5 and 10 have been canceled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hedler et al. US 2010/0013101 A1 (Hedler).
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In re claim 6, Hedler discloses (e.g. FIG. 3A) a chip package having electromagnetic interference shielding layer 18 (¶ 39) comprising:
a substrate 14 (on top side in FIG. 3A, see annotated in drawing above) which includes a first surface (bottom surface) provided with at least one blind hole (hole in 14) and a second surface (top surface) opposite to the first (bottom) surface;
at least one first circuit layer 12 which is arranged at the first (bottom) surface of the substrate 14, extending to a surface of an inner wall of the blind hole of the substrate (wiring 13 fills the hole in 14 together with layer 12 forms the “first circuit layer”, see annotated drawing above), and having a first (bottom) surface;
at least one second circuit layer 13 (middle layer above 14) which is disposed on the second (top) surface of the substrate 14; wherein the first circuit layer 12 is extending to and electrically connected with the second circuit layer 13 (middle layer) by the blind hole (via in 14) of the substrate;
at least one chip 1,2 electrically connected with and disposed on the first (bottom) surface of the first circuit layer 12;
a first insulating layer 6 which is arranged at the substrate 14, covering the chip 1,2, and provided with a first (bottom) surface;
at least one electromagnetic interference shielding layer 18 which is made of metal (¶ 39) and covering the first (bottom) surface of the first insulating layer 6 completely for preventing the first circuit layer 12, the second circuit layer 13 (middle layer), and the chip 1,2 from electromagnetic interference; wherein the electromagnetic interference shielding layer 18 is provided with a first (bottom) surface, and
a second insulating layer 14 (layer below 18) disposed on the first (bottom) surface of the electromagnetic interference shielding layer 18;
wherein the chip 1,2 is first electrically connected with the first (bottom) surface of the first circuit layer 12 which is extending to the second circuit layer 13 (middle layer) by the surface of the inner wall of the blind hole (via in 14) so that the chip 1,2 is electrically connected with the outside by the second circuit layer 13 (middle layer).
In re claim 8, Hedler discloses (e.g. FIG. 3A) wherein the second circuit layer 13 (middle layer 13) further includes a first (top) surface; wherein the second insulating layer 14 (middle layer 14 below 18) is provided with a first (bottom) surface; wherein the chip package further includes at least one first outer protective layer (bottommost layer 14) and at least one second outer protective (top most layer 14 or layer surrounding solder pads 15); wherein the first outer protective layer (bottommost layer 14) is disposed on the first (bottom) surface of the second insulating layer (middle layer 14 below 18); wherein the second outer protective layer (topmost layer 14 and layer surrounding 15) is arranged at the first (top) surface of the second circuit layer (middle layer 13) and provided with at least one opening (opening in topmost layer 14 and opening in top layer where pad 15 is located) for allowing the first (top) surface of the second circuit layer 13 to be exposed.
In re claim 9, Hedler discloses (e.g. FIG. 3A) wherein the opening of the second outer protective layer is provided with a solder ball 15+16 (located in opening in top layer where 15 is located) which is electrically connected with the first (top) surface of the second circuit layer (middle layer 13) so that the chip 1,2 is electrically connected with the outside by the solder ball 15+16.
Claims 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takano et al. US 2017/0077040 A1 (Takano).
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In re claim 6, Takano discloses (e.g. FIG. 2) a chip package having electromagnetic interference shielding layer 50 (¶ 22) comprising:
a substrate 10 which includes a first surface F11 provided with at least one blind hole 15 and a second surface F12 opposite to the first surface F11;
at least one first circuit layer 11+15 which is arranged at the first surface F11 of the substrate 10 (¶ 16), extending to a surface of an inner wall of the blind hole 15 of the substrate, and having a first surface (top surface);
at least one second circuit layer 12 which is disposed on the second surface F12 of the substrate 10 (¶ 17); wherein the first circuit layer 11+15 is extending to and electrically connected with the second circuit layer 12 by the blind hole 15 of the substrate;
at least one chip 20 electrically connected with and disposed on the first (top) surface of the first circuit layer 11+15 (wires 13 of chip 20 disposed on top of 11);
a first insulating layer 40 (¶ 21) which is arranged at the substrate 10, covering the chip 20 and provided with a first (top) surface;
at least one electromagnetic interference shielding layer 50 which is made of metal (¶ 22) and covering the first (top) surface of the first insulating layer 40 completely for preventing the first circuit layer 11+15, the second circuit layer 12, and the chip 20 from electromagnetic interference; wherein the electromagnetic interference shielding layer 50 is provided with a first (top) surface, and
a second insulating layer 60 (¶ 23) disposed on the first (top) surface of the electromagnetic interference shielding layer 50;
wherein the chip 20 is first electrically connected with the first (top) surface of the first circuit layer 11+15 which is extending to the second circuit layer 12 by the surface of the inner wall of the blind hole 15 so that the chip 20 is electrically connected with the outside by the second circuit layer 12 (¶ 17).
In re claim 7, Takano discloses (e.g. FIG. 2) wherein the electromagnetic interference shielding layer 50 is made of copper (¶ 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hedler as applied to claim 6 above, and further in view of Takano et al. (US 2017/0077040).
In re claim 7, Hedler discloses the clamed invention including a metallic electromagnetic interference shielding layer 18 (¶ 39). Hedler does not explicitly disclose the material of the shield layer is made of copper.
However, Takano a chip package (e.g. FIG. 2) comprising an electromagnetic interference shielding layer 50 outside an insulating resin 40 covering the chip 20, wherein a low resistance conductive material, e.g. copper, is used to form the shielding layer that is to be connected to ground potential to block electromagnetic noise (¶ 22).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Hedler shield layer 18 using copper as taught by Takano as a suitable electrically conductive material with low resistance for further connecting with ground potential to block electromagnetic noise as taught by Takano.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Takano as applied to claim 6 above, and further in view of Homma et al. US 201/0033086 (Homma).
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In re claim 8, Takano discloses (e.g. FIG. 2) wherein the second circuit layer 12 further includes a first (bottom) surface; wherein the second insulating layer 60a (see FIG. 5A-5B, ¶ 30) is provided with a first (top) surface; wherein the chip package further includes at least one first outer protective layer 60b (FIGs. 5A-5B, ¶ 30); wherein the first outer protective layer 60b is disposed on the first (top) surface of the second insulating layer 60a;
Takano discloses the second circuit layer 12 forms electrode pads for BGA (¶ 17). However, Takano does not explicitly disclose at least one second outer protective; wherein the second outer protective layer is arranged at the first (bottom) surface of the second circuit layer 12 and provided with at least one opening for allowing the first (bottom) surface of the second circuit layer 12 to be exposed.
However, Homma discloses (e.g. FIG. 1) a chip package comprising a substrate 11 having first circuit layer 12a,12b on a top surface and second circuit layer 13a,13b on the back surface, wherein a second outer protective layer 16 is arranged at the first (bottom) surface of the second circuit layer 13a,13b and provided with at least one opening for allowing the first (bottom) surface of the second circuit layer 13a,13b to be exposed (¶ 18), wherein the second outer protective layer 16 is a solder resist (¶ 18).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a solder resist layer on the bottom surface of the second circuit layer 12 taught by Takano to define the solder ball location and provide protection on the surface during solder ball formation as taught by Homma.
In re claim 9, Takano discloses (FIG. 2) solder balls electrically connected with the first (bottom) surface of the second circuit layer 12 so that the chip 20 is electrically connected with the outside by the solder ball (¶ 17).
Homma discloses (e.g. FIG. 1) wherein the opening of the second outer protective layer 16 is provided with a solder ball 2a,2b (¶ 20) which is electrically connected with the first (bottom) surface of the second circuit layer 13a,13b so that the chip 3A is electrically connected with the outside by the solder ball 2a,2b.
Response to Arguments
Applicant's arguments filed 4/24/2026 have been fully considered but they are not persuasive.
Applicant argues claimed invention differentiates from the prior art in that the circuit layer is “laid” on the inner wall of the hole rather than completely filling the hole (Remark, page 4), whereas Hedler and Takano both teach completely filling the via/hole (Remark, page 5)
This is not persuasive. Claim 6 merely recite “first circuit layer … extending to a surface of an inner wall of the blind hole”. This does not preclude completely filling of the blind hole. A circuit layer that completely fills the blind hole does “extend to a surface of an inner wall of the blind hole” and is considered to be “laid” on the inner wall of the hole.
More specifically, Hedler teaches forms a first circuit layer including conductor 12 and wiring 13 filled in the blind hole in layer 14. As such, the first circuit layer including wiring portion 13 that fills the blind hole and is “extending to a surface of an inner wall of the blind hole”.
Similarly, Takano teaches a first circuit layer 11+15 where the conductor via 15 fills the hole in substrate 10. Therefore, the first circuit layer 11+15 includes portion 15 that is “extending to a surface of an inner wall of the blind hole”.
Applicant further argued Takano and Homma teaching shielding layer and insulating layer wrapped around top and side surfaces in an enveloping manner while Applicant’s invention does not pertain to enveloping structure (Remark, pages 5-6).
This is not persuasive. No specific “non enveloping structure” is claimed. Claim package recites “electromagnetic interference shielding layer … covering the first surface of the first insulating layer completely, … and a second insulating layer disposed on the first surface of the electromagnetic interference shielding layer”. Takano’s shielding layer 50 covers the top surface of first insulating layer 50 completely and the second insulating layer 60 is disposed on the top surface of the shielding layer 50. Homma was not relied upon for teaching the shielding layer and the insulating layer structure.
Applicant further argues against Takano and Homma for using wire bonding 4 (Remark, page 6). However, present claimed invention does not structurally exclude wire bonding from being present in the package. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s argument the difference in the process, e.g. electroplating, in which the first circuit layer is formed on the inner wall (Remark, pages 6-7) is not persuasive since the claims are directed to the product. No specific “non-filling circuit layer” is claimed that would structurally distinguish over prior art teaching metal wiring present in the blind hole. In regard to the product by process language, since a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao and Sato et al., 190 USPQ 15 at 17 (CCPA 1976) (footnote 3). “[T]he lack of physical description in a product-by-process claim makes determination of the patentability of the claim more difficult, since in spite of the fact that the claim may recite only process limitations, it is the patentability of the product claimed and not of the recited process steps which must be established. We are therefore of the opinion that when the prior art discloses a product which reasonably appears to be either identical with or only slightly different than a product claimed in a product-by-process claim, a rejection based alternatively on either section 102 or section 103 of the statute is eminently fair and acceptable. As a practical matter, the Patent Office is not equipped to manufacture products by the myriad of processes put before it and then obtain prior art products and make physical comparisons therewith.” In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972). See also In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the final product per se which must be determined for patentability in a "product by, all of" claim, and not the patentability of the process, and that an old or obvious product, whether claimed in "product by process" claims or not, is not patentable. Note that Applicant has the burden of proof in such cases, as the above case law makes clear. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based upon the product itself. The patentability of a product does not depend on its method of production. If the product in product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product is made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
Applicant further argues against the combination of references due to their old publication year (Remark, page 8). This is not persuasive. In response to applicant's argument based upon the age of the references, contentions that the reference patents are old are not impressive absent a showing that the art tried and failed to solve the same problem notwithstanding its presumed knowledge of the references. See In re Wright, 569 F.2d 1124, 193 USPQ 332 (CCPA 1977).
Applicant argues against an excessive number of references, alleged three different references, used in combination (Remark, page 9).
This is not persuasive. Firstly, none of the rejection relied on a combination of three references. Claims 6 and 8-9 are anticipated by Helder; claim 7 is rejected over the combination of Hedler and Takano; claims 6-7 are further anticipated by Takano; and claims 8-9 are rejected over the combination of Takano and Homma.
Furthermore, reliance on a large number of references in a rejection does not, without more, weigh against the obviousness of the claimed invention. See In re Gorman, 933 F.2d 982, 18 USPQ2d 1885 (Fed. Cir. 1991).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning (Remark, page 9), it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Applicant argues it would not be obvious to modify Hedler using Takano and Homma to form the inner-wall laying structure (Remark, pages 9-10).
This is not persuasive. No rejection is made based on the combination of Hedler and Homma. Helder is combined with Takano to show it being obvious to form the shield layer using copper. Copper is known for its desirable property in a shielding layer as taught by Homma (¶ 22).
In response to applicant's argument that Takano and Homma do not recognize benefits of the invention (Remark, pages 9-110), the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
To the extent that applicant is arguing that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Applicant further argued against modifying Takano or Homma’s enveloping shielding layers and insulating layers with Helder’s non-enveloping shielding layer and insulating structure (Remark, page 10).
This is not persuasive. Such combination is not made in the rejection. Furthermore, no specific non-enveloping structure has been claimed. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s argument against use of wire bonding taught by the prior art (Remark, page 10) is not persuasive. Present claimed invention does not structurally exclude wire bonding from being present in the package. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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