DETAILED ACTION
This office action is in response to reply filed 12/22/2025.
Claims 6-9 are pending. Claims 1-5 and 10 have been canceled.
Election/Restrictions
Applicant’s election without traverse of invention Group I and Species II (FIGs. 6-9), encompassing claims 6-9, in the reply filed on 12/22/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hedler et al. US 2010/0013101 A1 (Hedler).
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In re claim 6, Hedler discloses (e.g. FIG. 3A) a chip package having electromagnetic interference shielding layer 18 (¶ 39) comprising:
a substrate 14 (on top side in FIG. 3A, see annotated in drawing above) which includes a first surface (bottom surface) provided with at least one blind hole (hole in 14) and a second surface (top surface) opposite to the first (bottom) surface;
at least one first circuit layer 12 which is arranged at the first (bottom) surface of the substrate 14, extending to a surface of an inner wall of the blind hole of the substrate (wiring 13 fills the hole in 14 together with layer 12 forms the “first circuit layer”, see annotated drawing above), and having a first (bottom) surface;
at least one second circuit layer 13 (middle layer above 14) which is disposed on the second (top) surface of the substrate 14; wherein the first circuit layer 12 is extending to and electrically connected with the second circuit layer 13 (middle layer) by the blind hole (via in 14) of the substrate;
at least one chip 1,2 electrically connected with and disposed on the first (bottom) surface of the first circuit layer 12;
a first insulating layer 6 which is arranged at the substrate 14, covering the chip 1,2, and provided with a first (bottom) surface;
at least one electromagnetic interference shielding layer 18 which is made of metal (¶ 39) and covering the first (bottom) surface of the first insulating layer 6 completely for preventing the first circuit layer 12, the second circuit layer 13 (middle layer), and the chip 1,2 from electromagnetic interference; wherein the electromagnetic interference shielding layer 18 is provided with a first (bottom) surface, and
a second insulating layer 14 (layer below 18) disposed on the first (bottom) surface of the electromagnetic interference shielding layer 18;
wherein the chip 1,2 is first electrically connected with the first (bottom) surface of the first circuit layer 12 which is extending to the second circuit layer 13 (middle layer) by the surface of the inner wall of the blind hole (via in 14) so that the chip 1,2 is electrically connected with the outside by the second circuit layer 13 (middle layer).
In re claim 8, Hedler discloses (e.g. FIG. 3A) wherein the second circuit layer 13 (middle layer 13) further includes a first (top) surface; wherein the second insulating layer 14 (middle layer 14 below 18) is provided with a first (bottom) surface; wherein the chip package further includes at least one first outer protective layer (bottommost layer 14) and at least one second outer protective (top most layer 14 or layer surrounding solder pads 15); wherein the first outer protective layer (bottommost layer 14) is disposed on the first (bottom) surface of the second insulating layer (middle layer 14 below 18); wherein the second outer protective layer (topmost layer 14 and layer surrounding 15) is arranged at the first (top) surface of the second circuit layer (middle layer 13) and provided with at least one opening (opening in topmost layer 14 and opening in top layer where pad 15 is located) for allowing the first (top) surface of the second circuit layer 13 to be exposed.
In re claim 9, Hedler discloses (e.g. FIG. 3A) wherein the opening of the second outer protective layer is provided with a solder ball 15+16 (located in opening in top layer where 15 is located) which is electrically connected with the first (top) surface of the second circuit layer (middle layer 13) so that the chip 1,2 is electrically connected with the outside by the solder ball 15+16.
Claims 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takano et al. US 2017/0077040 A1 (Takano).
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In re claim 6, Takano discloses (e.g. FIG. 2) a chip package having electromagnetic interference shielding layer 50 (¶ 22) comprising:
a substrate 10 which includes a first surface F11 provided with at least one blind hole 15 and a second surface F12 opposite to the first surface F11;
at least one first circuit layer 11+15 which is arranged at the first surface F11 of the substrate 10 (¶ 16), extending to a surface of an inner wall of the blind hole 15 of the substrate, and having a first surface (top surface);
at least one second circuit layer 12 which is disposed on the second surface F12 of the substrate 10 (¶ 17); wherein the first circuit layer 11+15 is extending to and electrically connected with the second circuit layer 12 by the blind hole 15 of the substrate;
at least one chip 20 electrically connected with and disposed on the first (top) surface of the first circuit layer 11+15 (wires 13 of chip 20 disposed on top of 11);
a first insulating layer 40 (¶ 21) which is arranged at the substrate 10, covering the chip 20 and provided with a first (top) surface;
at least one electromagnetic interference shielding layer 50 which is made of metal (¶ 22) and covering the first (top) surface of the first insulating layer 40 completely for preventing the first circuit layer 11+15, the second circuit layer 12, and the chip 20 from electromagnetic interference; wherein the electromagnetic interference shielding layer 50 is provided with a first (top) surface, and
a second insulating layer 60 (¶ 23) disposed on the first (top) surface of the electromagnetic interference shielding layer 50;
wherein the chip 20 is first electrically connected with the first (top) surface of the first circuit layer 11+15 which is extending to the second circuit layer 12 by the surface of the inner wall of the blind hole 15 so that the chip 20 is electrically connected with the outside by the second circuit layer 12 (¶ 17).
In re claim 7, Takano discloses (e.g. FIG. 2) wherein the electromagnetic interference shielding layer 50 is made of copper (¶ 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hedler as applied to claim 6 above, and further in view of Takano et al. (US 2017/0077040).
In re claim 7, Hedler discloses the clamed invention including a metallic electromagnetic interference shielding layer 18 (¶ 39). Hedler does not explicitly disclose the material of the shield layer is made of copper.
However, Takano a chip package (e.g. FIG. 2) comprising an electromagnetic interference shielding layer 50 outside an insulating resin 40 covering the chip 20, wherein a low resistance conductive material, e.g. copper, is used to form the shielding layer that is to be connected to ground potential to block electromagnetic noise (¶ 22).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Hedler shield layer 18 using copper as taught by Takano as a suitable electrically conductive material with low resistance for further connecting with ground potential to block electromagnetic noise as taught by Takano.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Takano as applied to claim 6 above, and further in view of Homma et al. US 201/0033086 (Homma).
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In re claim 8, Takano discloses (e.g. FIG. 2) wherein the second circuit layer 12 further includes a first (bottom) surface; wherein the second insulating layer 60a (see FIG. 5A-5B, ¶ 30) is provided with a first (top) surface; wherein the chip package further includes at least one first outer protective layer 60b (FIGs. 5A-5B, ¶ 30); wherein the first outer protective layer 60b is disposed on the first (top) surface of the second insulating layer 60a;
Takano discloses the second circuit layer 12 forms electrode pads for BGA (¶ 17). However, Takano does not explicitly disclose at least one second outer protective; wherein the second outer protective layer is arranged at the first (bottom) surface of the second circuit layer 12 and provided with at least one opening for allowing the first (bottom) surface of the second circuit layer 12 to be exposed.
However, Homma discloses (e.g. FIG. 1) a chip package comprising a substrate 11 having first circuit layer 12a,12b on a top surface and second circuit layer 13a,13b on the back surface, wherein a second outer protective layer 16 is arranged at the first (bottom) surface of the second circuit layer 13a,13b and provided with at least one opening for allowing the first (bottom) surface of the second circuit layer 13a,13b to be exposed (¶ 18), wherein the second outer protective layer 16 is a solder resist (¶ 18).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a solder resist layer on the bottom surface of the second circuit layer 12 taught by Takano to define the solder ball location and provide protection on the surface during solder ball formation as taught by Homma.
In re claim 9, Takano discloses (FIG. 2) solder balls electrically connected with the first (bottom) surface of the second circuit layer 12 so that the chip 20 is electrically connected with the outside by the solder ball (¶ 17).
Homma discloses (e.g. FIG. 1) wherein the opening of the second outer protective layer 16 is provided with a solder ball 2a,2b (¶ 20) which is electrically connected with the first (bottom) surface of the second circuit layer 13a,13b so that the chip 3A is electrically connected with the outside by the solder ball 2a,2b.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896