Prosecution Insights
Last updated: August 18, 2026
Application No. 18/226,849

Methods and Structure for Shielding Semiconductors From Ultraviolet Light

Non-Final OA §103
Filed
Jul 27, 2023
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
507 granted / 815 resolved
-5.8% vs TC avg
Strong +24% interview lift
Without
With
+24.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
60 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s)1, 4-14, 16, 21, 24-25, and 27 is/are rejected under 35 U.S.C. 103 as obvious over AU Optronics Corp. (TW 201214576 A) (“AU”) by means of machine translation, in view of… Zhang et al. (US 2017/0336831 A1) (“Zhang”), and/or Lim et al. (US 2017/0068128 A1) (“Lim), and/or Fechner et al. (US 2007/0232478 A1) (“Fechner”), and/or Brosnihan et al. (US 2012/0295058 A1) (“Brosnihan”). Regarding claim 1, AU teaches at least in figure 1F, a colored light shielding layer (108) over a semiconductor layer (106), wherein the colored light shielding layer (108) reduces exposure of the semiconductor layer (106) to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as disclosed by Applicant in their specification. Therefore, it must have this same characteristic. Therefore, it would have been obvious that the colored light shielding layer would reduce the exposure of the semiconductor layer to radiation having a wavelength of about 10nm to about 400nm because it is made with the same material claimed by Applicant in claim 3 and has about the same thickness as claimed by Applicant in claim 5. Pg. 2 at ¶ 11, where the thickness can be 20 nm which is very close to the claimed range of 0.1 to 10nm. MPEP 2144.05, where the ranges do not overlap, however, one would expect them to have the same properties. This is because both the prior art and the current application are directed to having a colored light shielding layer which blocks UV light. Compare application specification at ¶ 0046 and prior art pg. 1 at ¶ 4, where the colored light shielding layer of both is directed to blocking UV light. Thus, while the thickness does not overlap one clearly expects then to have the same properties. Therefore, this claim is obvious over the prior art.) AU does note teach: wherein the colored light shielding layer comprises NiO, Fe2O3, Mn3O4, CuO, Sb203, SnO, Cr203, Nd2O3, or a perovskite comprising Ca, Sr, or Bi. AU teaches: Other material such as TiO2 can be used as ultraviolet light shielding material. Pg. 2 at ¶ 5. Zhang teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be Sb2O3, SnO, etc. ¶ 0038. It would have been obvious to one of ordinary skill in the art to use one of the materials of Zhang in the device of AU as the materials of Zhang are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Lim teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be NiO, etc. ¶¶ 0065-68. It would have been obvious to one of ordinary skill in the art to use one of the materials of Lim in the device of AU as the materials of Lim are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Fechner teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be Fe2O3, etc. ¶ 0023. It would have been obvious to one of ordinary skill in the art to use one of the materials of Fechner in the device of AU as the materials of Fechner are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Brosnihan teaches: That material to block ambient light (which includes ambient UV light) in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be SnO, CuO, Cr2O3, , etc. ¶ 0124. It would have been obvious to one of ordinary skill in the art to use one of the materials of Brosnihan in the device of AU as the materials of Brosnihan are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Regarding claim 4, AU teaches at least in figure 1F, wherein the colored light shielding layer (108) is treated with ozone (this is a product-by-process limitation. According to Applicant’s ¶ 0050 the ozone allows for more oxygen atoms to be integrated into the colored shielding layer. The prior allows for more oxygen to be in the colored light shielding layer as it allows for Ti3O5. Therefore, the prior art teaches the resulting product.). Regarding claim 5, AU teaches at least in figure 1F, wherein the colored light shielding layer (108) has a thickness of about one angstrom (A) to about 100 angstroms (this limitation is obvious for the reasons given in claim 1 above). Regarding claim 6, AU teaches at least in figure 1F, wherein the semiconductor layer (106) has a channel length of about one nm to about 100 nm (adjusting the channel length of a transistor is basic knowledge of one of ordinary skill in the art. It is basic knowledge to one of ordinary skill in the semiconductor arts to change the channel length in order to increase current through the device versus minimizing the effects of short-channel effects. The channel length is a basic aspect of transistor design. Thus, while the prior art is silent with respect to channel length it would have been obvious to one of ordinary skill in the art to use routine skill in the art based upon the design requirements to create a transistor with the claimed channel length. Regarding claim 7, AU teaches at least in figure 1F, wherein the semiconductor layer (106) is formed from an oxide semiconductor (pg. 2 at ¶ 3). Regarding claim 8, AU teaches at least in figure 1F, wherein the oxide semiconductor is InGaZnO which is optionally doped with a metal (pg. 2 at ¶ 3). Regarding claim 12, AU teaches at least in figures 1F, and 2D, further comprising a dielectric layer (104/204). Regarding claim 13, AU teaches at least in figures 1F, and 2D, wherein the dielectric layer (104/204) comprises a high-k dielectric material, an oxide-nitride-oxide (ONO) material, or a ferroelectric material (pg. 3 at ¶ 2). Regarding claim 14, Claim 14 is rejected for the same reasons as claim 21 below. The difference between claim 14 and claim 21 is claim 14 uses the term “write line” and claim 21 uses the term “gate electrode”. These are interchangeable terms as the write line is being used as a gate electrode. Regarding claim 16, Claim 16 is rejected for the same reasons as claim 21 below, in that the gate dielectric 104 contacts the write line (gate electrode) (102). Regarding claim 21, AU teaches at least in figures 1F, a gate electrode (102) upon a substrate (100); a gate dielectric layer (104) separating the gate electrode (102) from a source electrode (S) and a drain electrode (D); a semiconductor layer (106) upon the gate dielectric layer (104); and a colored light shielding layer (108) over a semiconductor layer (106), wherein the colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm m (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as disclosed by Applicant in their specification. Therefore, it must have this same characteristic. Therefore, it would have been obvious that the colored light shielding layer would reduce the exposure of the semiconductor layer to radiation having a wavelength of about 10nm to about 400nm because it is made with the same material claimed by Applicant in claim 3 and has about the same thickness as claimed by Applicant in claim 5. Pg. 2 at ¶ 11, where the thickness can be 20 nm which is very close to the claimed range of 0.1 to 10nm. MPEP 2144.05, where the ranges do not overlap, however, one would expect them to have the same properties. This is because both the prior art and the current application are directed to having a colored light shielding layer which blocks UV light. Compare application specification at ¶ 0046 and prior art pg. 1 at ¶ 4, where the colored light shielding layer of both is directed to blocking UV light. Thus, while the thickness does not overlap one clearly expects then to have the same properties. Therefore, this claim is obvious over the prior art.) AU does note teach: wherein the colored light shielding layer comprises NiO, Fe2O3, Mn3O4, CuO, Sb203, SnO, Cr203, Nd2O3, or a perovskite comprising Ca, Sr, or Bi. AU teaches: Other material such as TiO2 can be used as ultraviolet light shielding material. Pg. 2 at ¶ 5. Zhang teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be Sb2O3, SnO, etc. ¶ 0038. It would have been obvious to one of ordinary skill in the art to use one of the materials of Zhang in the device of AU as the materials of Zhang are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Lim teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be NiO, etc. ¶¶ 0065-68. It would have been obvious to one of ordinary skill in the art to use one of the materials of Lim in the device of AU as the materials of Lim are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Fechner teaches: That material to block ultraviolet light in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be Fe2O3, etc. ¶ 0023. It would have been obvious to one of ordinary skill in the art to use one of the materials of Fechner in the device of AU as the materials of Fechner are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Brosnihan teaches: That material to block ambient light (which includes ambient UV light) in semiconductors can be the same material disclosed by AU (e.g. TiO2) or can be SnO, CuO, Cr2O3, , etc. ¶ 0124. It would have been obvious to one of ordinary skill in the art to use one of the materials of Brosnihan in the device of AU as the materials of Brosnihan are art recognized equivalent material to be used as ultraviolet light block material in semiconductor devices, and are recognized as being suitable for this same and intended purpose. MPEP 2144.06-07. Regarding claim 24, AU teaches at least in figures 1F, Claim 24 is rejected for the same reasons given in claims 2-3 above. Regarding claims 25, and 27, These claims are rejected for the same reasons as claim 7 above. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as obvious over AU, in view of Zhang, in view of Yukinobu et al. (US 2012/0223302 A1) (“Yukinobu”). Regarding claim 9, AU does not teach: wherein the oxide semiconductor is doped with the metal, and the metal is Ti, AI, Ag, W, Ce, Sn, V, or Sc. Yukinobu teaches: That IGZO, IZGO doped with Sn, ZnO, etc. are all obvious variants of each other for channel material. ¶ 0026. Thus, while AU is silent with respect to doped IGZO as the channel material the selection of a known art recognized equivalent material which is suitable for said intended purpose is obvious. MPEP 2144.06-07. Claim(s) 10-11, 15, and 22-24 is/are rejected under 35 U.S.C. 103 as obvious over AU, in view of Zhang, in view of Tsuda et al. (US 2017/0176826 A1) (“Tsuda”). Regarding claim 10, AU does not teach: further comprising a channel capping layer over the semiconductor layer. Tsuda teaches at least in figure 1: further comprising a channel capping layer (6) over the semiconductor layer (4). It would have been obvious to one of ordinary skill in the art to add the channel capping layer of Tsuda to the device of AU as the channel chapping layer would act as an etch stop during the manufacturing of the TFT device. ¶ 0063. Regarding claim 11, Tsuda teaches at least in figure 1: wherein the channel capping layer (6) comprises a silicon oxide, a silicon nitride, or another dielectric material (¶ 0081). Regarding claim 15, Claim 15 is rejected for the same reasons as claim 22 below. Regarding claim 22, Claim 22 is rejected for the same reasons as claim 10 above. Regarding claim 23, Tsuda teaches at least in figure 1: Further comprising an interlayer dielectric (ILD) layer (10) over the channel capping layer (6). Claim(s) 26 is/are rejected under 35 U.S.C. 103 as obvious over AU, in view of Zhang, in view of official notice. Regarding claim 26, AU and Zhang do not teach: interlayer dielectric (ILD) layer over the channel capping layer. However, ILDs are well-known and routinely used in the art. They are used to create an flat and/or insulating layer between devices and the interconnect wires. One of ordinary skill in the art will also use an ILD(s) layer in conjunction with CMP to create a flat layer with which to form layers above the device. Therefore, while the prior art does not explicitly show an ILD it would have been obvious to one of ordinary skill in the art to use routine skill in the art to form an such an ILD layer over the device of AU and Zhang to insulate the device from the necessary layers which will be formed over said device. Response to Arguments Applicant’s amendments have overcome the previous grounds of rejection. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the prior art above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Jul 27, 2023
Application Filed
Jan 23, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
Jun 11, 2026
Final Rejection mailed — §103
Jul 27, 2026
Response after Non-Final Action
Jul 30, 2026
Request for Continued Examination
Aug 03, 2026
Response after Non-Final Action
Aug 06, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
86%
With Interview (+24.3%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allowance rate.

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