DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A represented by figures 1-11 and claims 1-16 and 21-24 in the reply filed on December 31, 2025 is acknowledged.
Claims 14-16 are withdrawn from consideration. This is because claim 14s limitation
a colored light shielding layer (250) contacting the semiconductor layer (230) and located between the semiconductor layer (230) and the write line (the write line 210 – Applicant’s ¶ 0067 where the write line is the gate electrode 210) is not shown in figures 1-11. Rather what is shown is the color light shielding layer 250 is above the semiconductor layer 230 and above the gate electrode 210, and not between as claimed. Therefore, claims 14-16 are withdrawn from consideration
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 21, 2024 was considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-8, 12-13, 21, and 24 is/are rejected under 35 U.S.C. 102(a)(1)) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over AU Optronics Corp. (TW 201214576 A) (“AU”) by means of machine translation.
Regarding claim 1, AU teaches at least in figure 1F,
a colored light shielding layer (108) over a semiconductor layer (106),
wherein the colored light shielding layer (108) reduces exposure of the semiconductor layer (106) to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as claimed by Applicant in claim 3. Therefore, it must have this same characteristic); and
wherein the colored light shielding layer (108) has a white, black, red, yellow, or gray color (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as claimed by Applicant in claim 3. Therefore, it must have this same characteristic).
This rejection is under 35 USC § 102 and § 103, in the even that it is felt that this characteristic is not inherent in the material. In that case it would have been obvious that the colored light shielding layer would reduce the exposure of the semiconductor layer to radiation having a wavelength of about 10nm to about 400nm because it is made with the same material claimed by Applicant in claim 3 and has about the same thickness as claimed by Applicant in claim 5. Pg. 2 at ¶ 11, where the thickness can be 20 nm which is very close to the claimed range of 0.1 to 10nm. MPEP 2144.05, where the ranges do not overlap, however, one would expect them to have the same properties. This is because both the prior art and the current application are directed to having a colored light shielding layer which blocks UV light. Compare application specification at ¶ 0046 and prior art pg. 1 at ¶ 4, where the colored light shielding layer of both is directed to blocking UV light. Thus, while the thickness does not overlap one clearly expects then to have the same properties. Therefore, this claim is alternatively obvious over the prior art.
Regarding claim 2, AU teaches at least in figure 1F,
wherein the colored light shielding layer (108) is formed from a metal oxide film, a p-type oxide semiconductor, or a perovskite (pg. 2 at ¶ 5).
Regarding claim 3, AU teaches at least in figure 1F,
wherein the colored light shielding layer (108) comprises TiO2, NiO, Fe2O3, CO3O4, Mn3O4, CuO, Sb2O3, SnO, Cr2O3, a rare earth oxide, CeO2, Y2O3, Nd2O3, or a perovskite comprising Ca, Sr, or Bi (pg. 2 at ¶ 5).
Regarding claim 7, AU teaches at least in figure 1F,
wherein the semiconductor layer (106) is formed from an oxide semiconductor (pg. 2 at ¶ 3).
Regarding claim 8, AU teaches at least in figure 1F,
wherein the oxide semiconductor is InGaZnO which is optionally doped with a metal (pg. 2 at ¶ 3).
Regarding claim 12, AU teaches at least in figures 1F, and 2D,
further comprising a dielectric layer (104/204).
Regarding claim 13, AU teaches at least in figures 1F, and 2D,
wherein the dielectric layer (104/204) comprises a high-k dielectric material, an oxide-nitride-oxide (ONO) material, or a ferroelectric material (pg. 3 at ¶ 2).
Regarding claim 21, AU teaches at least in figures 1F,
a gate electrode (102) upon a substrate (100);
a gate dielectric layer (104) separating the gate electrode (102) from a source electrode (S) and a drain electrode (D);
a semiconductor layer (106) upon the gate dielectric layer (104); and
a colored light shielding layer (108) over a semiconductor layer (106), wherein the colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm m (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as claimed by Applicant in claim 3. Therefore, it must have this same characteristic); and
wherein the colored light shielding layer (108) has a white, black, red, yellow, or gray color (pg. 2 at ¶¶ 5-6, where the colored light shielding layer can be formed of the same material as claimed by Applicant in claim 3. Therefore, it must have this same characteristic).
This rejection is under 35 USC § 102 and § 103, in the even that it is felt that this characteristic is not inherent in the material. In that case it would have been obvious that the colored light shielding layer would reduce the exposure of the semiconductor layer to radiation having a wavelength of about 10nm to about 400nm because it is made with the same material claimed by Applicant in claim 3 and has about the same thickness as claimed by Applicant in claim 5. Pg. 2 at ¶ 11, where the thickness can be 20 nm which is very close to the claimed range of 0.1 to 10nm. MPEP 2144.05, where the ranges do not overlap, however, one would expect them to have the same properties. This is because both the prior art and the current application are directed to having a colored light shielding layer which blocks UV light. Compare application specification at ¶ 0046 and prior art pg. 1 at ¶ 4, where the colored light shielding layer of both is directed to blocking UV light. Thus, while the thickness does not overlap one clearly expects then to have the same properties. Therefore, this claim is alternatively obvious over the prior art.
Regarding claim 24, AU teaches at least in figures 1F,
Claim 24 is rejected for the same reasons given in claims 2-3 above.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as obvious over AU.
Regarding claim 4, AU teaches at least in figure 1F,
wherein the colored light shielding layer (108) is treated with ozone (this is a product-by-process limitation. According to Applicant’s ¶ 0050 the ozone allows for more oxygen atoms to be integrated into the colored shielding layer. The prior allows for more oxygen to be in the colored light shielding layer as it allows for Ti3O5. Therefore, the prior art teaches the resulting product.).
Regarding claim 5, AU teaches at least in figure 1F,
wherein the colored light shielding layer (108) has a thickness of about one angstrom (A) to about 100 angstroms (this limitation is obvious for the reasons given in claim 1 above).
Regarding claim 6, AU teaches at least in figure 1F,
wherein the semiconductor layer (106) has a channel length of about one nm to about 100 nm (adjusting the channel length of a transistor is basic knowledge of one of ordinary skill in the art. It is basic knowledge to one of ordinary skill in the semiconductor arts to change the channel length in order to increase current through the device versus minimizing the effects of short-channel effects. The channel length is a basic aspect of transistor design. Thus, while the prior art is silent with respect to channel length it would have been obvious to one of ordinary skill in the art to use routine skill in the art based upon the design requirements to create a transistor with the claimed channel length.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as obvious over AU, in view of Yukinobu et al. (US 2012/0223302 A1) (“Yukinobu”).
Regarding claim 9, AU does not teach:
wherein the oxide semiconductor is doped with the metal, and the metal is Ti, AI, Ag, W, Ce, Sn, V, or Sc.
Yukinobu teaches:
That IGZO, IZGO doped with Sn, ZnO, etc. are all obvious variants of each other for channel material. ¶ 0026.
Thus, while AU is silent with respect to doped IGZO as the channel material the selection of a known art recognized equivalent material which is suitable for said intended purpose is obvious. MPEP 2144.06-07.
Claim(s) 10-11, and 22-24 is/are rejected under 35 U.S.C. 103 as obvious over AU, in view of Tsuda et al. (US 2017/0176826 A1) (“Tsuda”).
Regarding claim 10, AU does not teach:
further comprising a channel capping layer over the semiconductor layer.
Tsuda teaches at least in figure 1:
further comprising a channel capping layer (6) over the semiconductor layer (4).
It would have been obvious to one of ordinary skill in the art to add the channel capping layer of Tsuda to the device of AU as the channel chapping layer would act as an etch stop during the manufacturing of the TFT device. ¶ 0063.
Regarding claim 11, Tsuda teaches at least in figure 1:
wherein the channel capping layer (6) comprises a silicon oxide, a silicon nitride, or another dielectric material (¶ 0081).
Regarding claim 22,
Claim 22 is rejected for the same reasons as claim 10 above.
Regarding claim 23, Tsuda teaches at least in figure 1:
Further comprising an interlayer dielectric (ILD) layer (10) over the channel capping layer (6).
Conclusion
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/VINCENT WALL/Primary Examiner, Art Unit 2898