DETAILED ACTION
This Office action is in response to the election filed 12 January 2026. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-11, in the reply filed on 12 January 2026 is acknowledged.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable US 2022/0376117 A1 to Kim (hereinafter “Kim”).
Regarding independent claim 1, Kim (Fig. 6) discloses a display device comprising:
a substrate 100 (¶ 0103);
a transistor TFT” (¶ 0103) disposed on the substrate, wherein the transistor includes an active layer 220/210 (¶ 0104) including a first active area 210a/220c1/210b (¶ 0104) and a second active area 210d/220c2/210b (¶ 0104), wherein the first active area includes a first drain area 210a (¶ 0104), a source area 210b (¶ 0104), and a first channel area 220c1 (¶ 0104) located between the first drain area and the source area, and the second active area includes the source area 210b, a second drain area 210d (¶ 0105), and a second channel area 220c2 (¶ 0105) located between the source area and the second drain area;
a gate insulating layer 112 (¶ 0104) disposed on the active layer;
a second charge layer CIR1/CIR2 (¶ 0107) defined at the interface between the first channel area 220c1 and the gate insulating layer 112 to be adjacent to the first drain area 210a and at the interface between the second channel area 220c2 and the gate insulating layer 112 to be adjacent to the second drain area 210d,
In the embodiment of Fig. 6, Kim fails to expressly disclose a first charge layer defined at an interface between the first channel area and the gate insulating layer to be adjacent to the source area and at an interface between the second channel area and the gate insulating layer to be adjacent to the source area; and wherein the second charge layer has a charge opposite to a charge of the first charge layer.
In a different embodiment, Kim (Fig. 4) discloses a first charge layer CIR1/CIR2 (¶ 0085, 87) defined at an interface between the first channel area 220c1 (¶ 0085) and the gate insulating layer 112 (¶ 0085) to be adjacent to the source area 210b (¶ 0086) and at an interface between the second channel area 220c2 (¶ 0086) and the gate insulating layer 112 to be adjacent to the source area 210b. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of Kim to include a first charge layer as disclosed in the embodiment of Fig. 4, for the purpose of reducing leakage current (¶ 0100). Additionally, it would have been obvious to one of ordinary skill in the art to provide a second charge layer having a charge opposite to a charge of the first layer since there are only two possible charge combinations (i.e., same charge, opposite charge) and a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, with a reasonable expectation of success. MPEP 2143(I)(E).
Regarding claim 2, Kim discloses the display device of claim 1, wherein the second charge layer shifts a threshold voltage of the transistor in one of a positive direction and a negative direction, and the first charge layer shifts the threshold voltage of the transistor in the other of the positive direction and the negative direction (these limitations are considered functional language that does not structurally distinguish the claimed invention or the prior art; Kim discloses the structure as recited in the claim as currently drafted, thus the structure of Kim is presumed to capable of the functionally defined limitations oof the claimed device. MPEP 2114(I).
Regarding claim 3, Kim discloses the display device of claim 1, wherein the first charge layer CIR1/CIR2 (Fig. 4) and the second charge layer CIR1/CIR2 (Fig. 6) are spaced apart from each other.
Regarding claim 4, Kim (Figs. 4, 6) discloses the display device of claim 1, wherein the transistor includes a first gate electrode 230a (¶ 0104) overlapping the first channel area 220c1 and a second gate electrode 230b (¶ 0099) overlapping the second channel area 220c2, and wherein the first gate electrode and the second gate electrode are electrically connected to each other (Fig. 5).
Regarding claim 5, Kim (Fig. 6) discloses the display device of claim 4, wherein the transistor includes: a first sub-transistor defined by the first active area 210a/220c1/210b and the first gate electrode 230a; and a second sub-transistor defined by the second active area 210b/220c2/210d and the second gate electrode 230b, and wherein the first sub-transistor and the second sub-transistor are connected to each other (Figs. 5, 6).
Regarding claim 6, Kim (Figs. 4, 6) discloses the display device of claim 4, wherein each of the first charge layer CIR1/CIR2 (Fig. 4) and the second charge layer CIR1/CIR2 (Fig. 6) overlaps the first gate electrode 230a and the second gate electrode 230b when viewed in a thickness direction of the substrate.
Regarding claim 7, Kim discloses the display device of claim 1, wherein each of the first drain area, the source area, and the second drain area is doped with P-type impurity ions (¶ 0107 - P-type transistor).
Regarding claim 8, Kim discloses the display device of claim 7, wherein the second charge layer has a negative charge (¶ 0107). Kim does not expressly disclose the first charge layer has a positive charge. However, it would have been obvious to one of ordinary skill in the art to provide a positive charge in the first charge layer since there are only two possible charges (i.e., positive, negative) and a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, with a reasonable expectation of success. MPEP 2143(I)(E).
Regarding claim 9, Kim discloses the display device of claim 1, wherein each of the first drain area, the source area, and the second drain area is doped with N-type impurity ions (¶ 0107 - N-type transistor).
Regarding claim 10, Kim discloses the display device of claim 9, wherein the second charge layer has a positive charge (¶ 0107). Kim does not expressly disclose the first charge layer has a negative charge. However, it would have been obvious to one of ordinary skill in the art to provide a negative charge in the first charge layer since there are only two possible charges (i.e., positive, negative) and a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, with a reasonable expectation of success. MPEP 2143(I)(E).
Regarding claim 11, Kim discloses the display device of claim 1, wherein the active layer 220/210 includes a silicon semiconductor (¶ 0068).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2011/0140116 A1 to Morosawa et al. disclosing a thin film transistor with a charge layer and shifted threshold voltage; 2016/0027814 A1 to Jin et al. disclosing thin film transistors with doped areas adjacent to source/drain regions.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
24 February 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813