DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed 8/13/2026 was disapproved. An updated POA with the new applicant’s name along with the Terminal Disclaimer form. No additional fee is required with the resubmission (per OPLC 8/24/2026).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,810,960. Although the claims at issue are not identical, they are not patentably distinct from each other because the currently recited broader claims are fully covered by the already patent claims.
Claims 2-6, 8-13, 15-20 are also rejected as being dependent on claims 1, 7 and 14 respectively.
U.S. Patent No. 11,810,960
Current Application
1. A semiconductor device, comprising: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a source/drain (S/D) region disposed adjacent to the gate structure; a contact structure disposed on the S/D region, wherein the contact structure comprises a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer; and a dipole layer disposed at an interface between the ternary compound layer and the S/D region.
1. A semiconductor device, comprising: a gate structure disposed on first and second fin structures; a merged source/drain (S/D) region disposed on the first and second fin structures; and a contact structure disposed on the merged S/D region, wherein the contact structure comprises ternary compound clusters disposed on the merged S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound clusters and the merged S/D region, wherein interfaces between the WFM silicide layer and the S/D region separate the ternary compound cluster from each other, and a contact plug disposed on the WFM silicide layer.
3. The semiconductor device of claim 1, wherein the ternary compound layer comprises a zirconium-based ternary compound.
2. The semiconductor device of claim 1, wherein the ternary compound clusters comprise a zirconium-based ternary compound.
7. A method, comprising: forming a fin structure on a substrate; forming a source/drain (S/D) region on the fin structure; forming a contact opening on the S/D region; forming a doped work function metal (WFM) silicide layer comprising metal dopants within the contact opening; forming a ternary compound layer between the doped WFM silicide layer and the S/D region; and forming a contact plug within the contact opening.
14. A method, comprising: forming a gate structure disposed on a substrate; forming a source/drain (S/D) region on the substrate; and forming a contact structure on the S/D region, wherein forming the contact structure comprises: depositing a dopant source layer on the S/D region; depositing a metal layer in contact with the dopant source layer; and depositing a contact plug on the metal layer.
Response to Arguments
Applicant’s arguments/amendment with respect to claims 1-20 have been considered. However, upon further consideration, the Double Patenting rejection for claims 1-3, 5-21 is still outstanding.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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