DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 01/19/2026 is acknowledged. The traversal is on the ground(s) that there is no serious search or examination burden. This is not found persuasive because the method of Group II (now cancelled) would require specific method process sequences that may require different fields of search beyond what would be required for Group I. Furthermore, the extensive difference in method would require different statuses in classification and divergence of subject matter. Finally, prior art applicable to Group I would not likely be applicable to that of Group II as Group II requires very specific method steps and sequences outside the standard practices found within the art.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada et al. (U.S. Publication No. 2021/0134801 A1; hereinafter Harada)
With respect to claim 1, Harada discloses a semiconductor structure, comprising: a logic device [300]; a first contact [330] connected to the logic device; a first power rail [1001/356] over the logic device and connected to the logic device; a second power rail [356] (connected to gate electrode based on Fig 7) over the logic device; and a transistor [200] having a channel region comprising indium, gallium, zinc, and oxygen (see ¶[0140-0142) over the second power rail and connected to the second power rail (see Figure 12).
With respect to claim 2, Harada discloses a first storage element [100] connected between the second power rail and the transistor (see Figure 12).
With respect to claim 3, Harada discloses wherein the first storage element comprises: a first conductive layer [110]; an insulator layer [130] over the first conductive layer; and a second conductive layer [120] over the insulator layer (see Figure 12).
With respect to claim 5, Harada discloses wherein: the transistor comprises at least one of a bottom gate fin field effect transistor (finFET) device, a top gate finFET device, or a planar device (see Figure 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Gomes et al. (U.S. Publication No. 2023/0197654 A1; hereinafter Gomes). With respect to claim 4, Harada fails to explicitly disclose the first storage element comprises at least one of a resistive random access memory storage element, a dynamic random access memory storage element, a magnetic random access memory storage element, or a ferromagnetic random access memory storage element, however does exhibits the structural characteristics of a dynamic random access memory storage (see Figure 12). In the same field of endeavor, Gomes discloses a DRAM 1T-1C cell (See ¶[0062-0063]). Implementation of a DRAM device with ferromagnetic capacitors as taught by Gomes are equivalent structures to that of Harada, therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the DRAM structures and ferroelectric capacitors of Gomes can be implemented interchangably with no functionality loss (see Gomes Figure 6). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that that the combination of references would arrive at the claimed invention
With respect to claim 7, Harada fails to disclose comprising: a second storage element under the logic device. In the same field of endeavor, Gomes teaches a second storage element [501’] under the logic device. Implementation of a backside storage structure as taught by Gomes allows for increased capability of the memory structure, allowing for a single logic array to control multiple memory banks (see Gomes ¶[0060]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Or-Bach et al. (U.S. Publication No. 2020/0243487 A1; hereinafter Or-Bach).
With respect to claim 6, Harada discloses a seal ring adjacent the logic device and the transistor. In the same field of endeavor, Or-Bach teaches utilizing seal rings (see ¶[0129] and Figure 7C). Implementation of seal-rings allows for thermal dissipation and protection from damage to surrounding structures (See Or-Bach ¶[0129]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gomes in view of Harada.
With respect to claim 16, Gomes discloses a semiconductor structure, comprising: a carrier wafer comprising: a substrate layer [406]; a first dielectric layer [405]; and a first conductive structure [410] embedded in the first dielectric layer; and a device wafer comprising: a logic device [381] connected to the first conductive structure; a backside contact [510] connected to the logic device; a second dielectric layer [301] under the logic device and bonded to the first dielectric layer of the carrier wafer; a third dielectric layer [303] over the logic device; a fourth dielectric layer [303] over the logic device; and a memory device [391], wherein the memory device comprises a transistor having a channel layer comprising indium, gallium, zinc, and oxygen (see ¶[0037]).
Gomes fails to explicitly disclose a first power rail embedded in the third dielectric layer and connected to the logic device; a second power rail embedded in the fourth dielectric layer; a memory device over the second power rail and connected to the second power rail. In the same field of endeavor, Harada teaches a first power rail [1001/356] embedded in the third dielectric layer [352] and connected to the logic device [300]; a second power rail [356] (connected to gate electrode based on Fig 7) embedded in the fourth dielectric layer [354]; a memory device [200] over the second power rail and connected to the second power rail (See Figure 12). Implementation of the memory device and power rail orientation of Harada allows for a low off-state current and thereby can retain stored content for longer and not required to perform refresh operations, reducing power consumption (see ¶[0274]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, the combination of Gomes and Harada discloses wherein the memory device comprises: a first storage element [100] connected between the second power rail and the transistor (see Harada Figure 12).
With respect to claim 18, the combination of Gomes and Harada discloses wherein the first storage element comprises: a first conductive layer [110]; an insulator layer [130] over the first conductive layer; and a second conductive layer [120] over the insulator layer (see Figure 12).
With respect to claim 19, the combination of Gomes and Harada discloses wherein the carrier wafer comprises: a second storage element [20’] (see Gomes Figure 5).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gomes in view of Harada as applied to claim 19 above, and further in view of Or-Bach.
With respect to claim 20, the combination of Gomes and Harada discloses a seal ring adjacent the logic device and the memory device, wherein: a first portion of the seal ring is in the carrier wafer, and a second portion of the seal ring is in the device wafer. In the same field of endeavor, Or-Bach teaches utilizing seal rings across multiple layers of the device (see ¶[0129] and Figure 7C). Implementation of seal-rings allows for thermal dissipation and protection from damage to surrounding structures (See Or-Bach ¶[0129]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 21-2 and 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Chiang et al. (U.S. Publication No. 2021/0305252 A1; hereinafter Chiang).
With respect to claim 21, Harada discloses a semiconductor structure, comprising: a logic device [300] comprising a source/drain region [314a]; a first power rail [1001/356] over the logic device and coupled to the source/drain region; a second power rail [366] over the first power rail; and a memory device [100/200] over the second power rail and coupled to the second power rail (see Figure 12; [366] couples [300] to memory devices above).
Harada fails to disclose the source/drain region between a first channel semiconductor layer and a second channel semiconductor layer. In the same field of endeavor, Chiang teaches a source/drain region [260/382/388] between a first channel semiconductor layer [215] and a second channel semiconductor layer [215] with a first power rail coupled to [390] (see Figure 24B; note source/drain region does not contain any structural limitations and therefore can be considered all elements pertaining to the source/drain including the contact structures). Implementation of a gate all around logic device as an alternative for the planar device of Harada allows for increased density of transistors driven by smaller device pitches while allowing for less power rails to drive the FETs (See ¶[0019]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention.
With respect to claim 22, the combination of Harada and Chiang discloses wherein the memory device comprises: a transistor [200] over the second power rail; and a first storage element [100] over the transistor, coupled to the transistor, and coupled to the second power rail. (see Harada Figure 12)
With respect to claim 23, the combination of Harada and Chiang discloses wherein the transistor has a channel layer comprising indium, gallium, zinc, and oxygen (see Harada ¶[0140-0142).
With respect to claim 25, the combination of Harada and Chiang discloses wherein the logic device comprises an end spacer [318] disposed between the source/drain region and a gate electrode layer [316] (See Harada Figure 12; also Chiang end spacer [247], gate electrode [240’] Figure 12B).
With respect to claim 26, the combination of Harada and Chiang discloses wherein an uppermost surface of the source/drain region, facing the first power rail, is above an uppermost surface of a gate electrode layer of the logic device facing the first power rail (See Figure 24B). With respect to claim 27, the combination of Harada and Chiang discloses comprising: a gate contact [203] between the second power rail and a gate electrode [260] of the memory device (see Harada ¶[0319]; limitation does not require physical connection within the circuit of the devices in sequence, “between” can be physically between in a direction).
With respect to claim 28, the combination of Harada and Chiang discloses wherein the memory device comprises: the gate electrode [260]; a gate dielectric layer [250] over the gate electrode; and a channel layer [230] over the gate dielectric layer (see Harada Figure 13A).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Chiang as applied to claim 24 above, and further in view of Iikubo et al. (U.S. Publication No. 2023/0144044 A1; hereinafter Iikubo)
With respect to claim 24, the combination of Harada and Chiang discloses comprising: a first conductive structure over the first storage element; a second conductive structure between the first storage element and the first conductive structure to couple the first storage element to the first conductive structure; and a third conductive structure between the first conductive structure and the second power rail to couple the first conductive structure and the second power rail, but does disclose routing of conductive structures to connect the second power rail and first storage element (See Harada Figure 12). In the same field of endeavor, Iikubo teaches a first conductive structure [153] over the first storage element [100]; a second conductive structure [112] between the first storage element and the first conductive structure to couple the first storage element to the first conductive structure; and a third conductive structure [248] between the first conductive structure and the second power rail to couple the first conductive structure and the second power rail (See Iikubo Figure 12). Allowing the wiring routing of Iikubo allows for inhibition of electrostatic breakdown of transistors and the semiconductor devices (see ¶[0361]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamazaki et al. (U.S. Publication No. 2021/0384326 A1) discloses a stacked memory and logic device
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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