DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I (claims 1-11 and 14-20) in the reply filed on 12/18/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 12 and 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/18/2025.
Claim Objections
Claim 8 is objected to because of the following informalities: in line 1, "structure" should be amended to read -method-. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano et al (US 2016/0020289 and Nakano hereinafter) in view of Tan et al (US 2017/0316935 and Tan hereinafter).
As to claims 1-7: Nakano discloses [claim 1] a method of forming a structure for a field-effect transistor (Fig. 3; [0086]), the method comprising: providing a semiconductor substrate (10; [0079]), wherein the semiconductor substrate (10) comprises a wide bandgap semiconductor material (SiC; [0079]); and forming a first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer; [0116]) on the surface (sidewalls of trench 8 formed in the substrate 10; [0076]) of the semiconductor substrate (10); [claim 2] further comprising: forming a second gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the second gate dielectric would be an upper layer of the multilayer; [0116]) on the first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer); and forming a gate electrode (16; [0085] and [0095]), wherein the first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer) and the second gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the second gate dielectric would be an upper layer of the multilayer) are disposed between the gate electrode (16) and the surface (sidewalls of trench 8 formed in the substrate 10) of the semiconductor substrate (10); [claim 3] wherein the wide bandgap semiconductor material comprises silicon carbide (10 can be SiC; [0079]); [claim 5] wherein the semiconductor substrate (10) includes a trench (8; [0084]) having a plurality of sidewalls (vertical sidewalls), and the surface (sidewalls of trench 8 formed in substrate 10) is inside the trench (8); [claim 6] further comprising: forming a second gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the second gate dielectric would be an upper layer of the multilayer; [0116]) on the first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer); and forming a gate electrode (16; [0085] and [0095]) inside the trench (8), wherein the second gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the second gate dielectric would be an upper layer of the multilayer) is disposed between the gate electrode (16) and the first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer); [claim 7] wherein the gate electrode (16) is disposed inside the trench (8), and the first gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the first gate dielectric would be a lower layer of the multilayer) and the second gate dielectric layer (17 can be multilayer, e.g. SiO2/AlON/SiO2, and the second gate dielectric would be an upper layer of the multilayer) are disposed between the gate electrode (16) and the sidewalls of the trench (8).
Nakano fails to expressly disclose [claim 1] cleaning a surface of the semiconductor substrate with atomic layer etching; [claim 4] wherein the surface of the semiconductor substrate is cleaned before forming the first gate dielectric layer.
Tan discloses in [0045] that atomic layer etching can be used on substrates that comprise semiconductor materials (such as silicon carbide) which have trenches formed therein.
Therefore, Tan discloses [claim 1] cleaning a surface of the semiconductor substrate with atomic layer etching (Fig. 1; [0043]-[0047]); [claim 4] wherein the surface of the semiconductor substrate is cleaned before forming the first gate dielectric layer (the process of Tan can be applied to a trench after it is provided and before layers are formed thereon; [0036]-[0040] and [0056]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to apply the method of cleaning a surface that comprises carbon, such as a trench in a silicon carbide substrate, of Tan to the method of Nakano prior to forming insulating layers in the trench in the SiC substrate in order to provide a trench sidewall surface that is smooth and clean ([0040], [0045], and [0051]).
Claims 8, 9, 11, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan as applied to claims 1 and 6 above, and further in view of Zhong (CN 109585564 and Zhong hereinafter; a machine translation is used as an English language equivalent).
As to claims 8, 9, 11, 15, and 17: Although the method disclosed by Nakano in view of Tan shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
[claim 8] wherein the second gate dielectric layer is thicker than the first gate dielectric layer; [claim 9] wherein the first gate dielectric layer comprises silicon dioxide, and the second gate dielectric layer comprises silicon dioxide; [claim 11] wherein the first gate dielectric layer has a thickness in a range of 2.5 nanometers to 10 nanometers; [claim 15] wherein forming the first gate dielectric layer on the surface of the semiconductor substrate comprises: depositing the first gate dielectric layer on the surface of the semiconductor substrate; [claim 17] further comprising: forming a second gate dielectric layer on the first gate dielectric layer.
Zhong discloses a SiC based transistor [claim 8] wherein the second gate dielectric layer (Fig. 1; high-power deposited SiO2; [0058]-[0062]) is thicker (10 nm – 25 nm; [0062]) than the first gate dielectric layer (low-power deposited SiO2 has a thickness of 5 nm – 10 nm; [0058]-[0062]); [claim 9] wherein the first gate dielectric layer (low-power deposited SiO2; [0058]-[0062]) comprises silicon dioxide (SiO2), and the second gate dielectric layer (high-power deposited SiO2; [0058]-[0062]) comprises silicon dioxide (SiO2); [claim 11] wherein the first gate dielectric layer (low-power deposited SiO2) has a thickness in a range of 2.5 nanometers to 10 nanometers (low-power deposited SiO2 has a thickness of 5 nm – 10 nm; [0058]-[0062]); [claim 15] wherein forming the first gate dielectric layer (low-power deposited SiO2; [0058]-[0062]) on the surface of the semiconductor substrate (SiC) comprises: depositing (through PECVD; [0059]) the first gate dielectric layer (low-power deposited SiO2) on the surface of the semiconductor substrate (SiC); [claim 17] further comprising: forming a second gate dielectric layer (high-power deposited SiO2; [0058]-[0062]) on the first gate dielectric layer (low-power deposited SiO2).
Therefore, given the teachings of Zhong, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nakano in view of Tan by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Zhong, by employing a gate dielectric that comprises silicon dioxide formed by using different parameters of a PECVD process to obtain different thicknesses, where the first gate silicon dioxide layer has a thickness within the claimed range, in order to provide a transistor with reduced on-resistance, improved channel mobility, and enhanced reliability ([0072]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan as applied to claim 6 above, and further in view of Hamamura et al (US 2013/0234163 and Hamamura hereinafter).
Although the method disclosed by Nakano in view of Tan shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
wherein the first gate dielectric layer comprises aluminum oxide, and the second gate dielectric layer comprises silicon dioxide.
Nakano combined with Tan discloses in [0116] that gate dielectric 17 can be multilayer, e.g. SiO2/AlON/SiO2. The first gate dielectric isn’t limited by the claims to be in direct contact with the substrate and thus can be the middle layer of the multilayer and the second gate dielectric can be the top layer of the multilayer while the lower layer of the multilayer can be interpreted as an interfacial layer.
Hamamura discloses in [0024] and Fig. 1 that aluminum oxide can be used as a high-k metal oxide that is between a silicon oxide lower layer and a silicon oxide upper layer.
Therefore, replacing AlON of Nakano with aluminum oxide of Hamamura would result in the first gate dielectric being aluminum oxide, the second gate dielectric being silicon dioxide, and the interfacial layer being silicon dioxide.
Therefore, given the teachings of Hamamura, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nakano in view of Tan by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Hamamura, by employing a gate dielectric that comprises aluminum oxide and silicon dioxide, where the first gate dielectric layer is aluminum oxide and the second gate dielectric layer is silicon dioxide in order to provide a transistor with high mobility and high reliability ([0016]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan as applied to claim 1 above, and further in view of Tsuji et al (US 2024/0079275 and Tsuji hereinafter).
Although the method disclosed by Nakano in view of Tan shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
further comprising: annealing the first gate dielectric layer in an ambient including nitrous oxide.
Nakano combined with Tan discloses in [0116] that gate dielectric 17 can be multilayer, e.g. SiO2/AlON/SiO2. The first gate dielectric can be interpreted to be the first SiO2 layer, which is formed by a thermal oxidation process ([0017]).
Tsuji discloses in [0046] that a first SiO2 film formed on the surface of a trench sidewall in a SiC substrate can be annealed in a nitrous oxide atmosphere after it is formed and before the next gate dielectric layer is formed.
Therefore, given the teachings of Tsuji, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nakano in view of Tan by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Tsuji, by employing an annealing step in a nitrous oxide atmosphere after forming a silicon dioxide film through thermal oxidation of a SiC trench sidewall surface in order to provide a transistor with a passivated surface between the silicon dioxide and the substrate ([0046]).
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan in view of Zhong as applied to claims 15 and 17 above, and further in view of Yang et al (CN 113555287 and Yang hereinafter; a machine translation is used as an English language equivalent).
As to claims 16 and 19: Although the method disclosed by Nakano in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 11 above), it fails to expressly disclose:
[claim 16] wherein the first gate dielectric layer is deposited at a substrate temperature in a range between 25°C and 400°C; [claim 19] wherein the second gate dielectric layer is formed at a higher substrate temperature than the first gate dielectric layer.
Zhong discloses in [0060] forming silicon dioxide layers of different thicknesses by modifying parameters of a PECVD process. The first gate dielectric layer of SiO2 is formed using a low-power PECVD process and the second gate dielectric layer of SiO2 is formed using a high-power PECVD process.
Yang discloses in [0100] that a SiO2 film formed using a power of 50W and a temperature of 150°C produces a film with thickness of 170 nm. Yang discloses in [0134] that a SiO2 film formed using a power of 100W and a temperature of 250°C produces a film of 250 nm. Therefore, Yang discloses conditions where a thinner first SiO2 film is deposited at a lower temperature and lower power than the thicker second SiO2 film formed using a higher power.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to adjust the PECVD parameters to form the SiO2 films, as indicated by Zhong, with different thicknesses by adjusting the power and temperature such that the first gate dielectric is formed using a lower temperature than the second gate dielectric using a temperature that is within the claimed range in order to yield the gate dielectric of sufficient thickness and quality to provide desired electrical isolation for the transistor.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan in view of Zhong as applied to claim 17 above, and further in view of Sugahara (JP 2018200919 and Sugahara hereinafter; a machine translation is used as an English language equivalent).
Although the method disclosed by Nakano in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 11 above), it fails to expressly disclose:
wherein forming the second gate dielectric layer on the first gate dielectric layer comprises: depositing a high temperature oxide by low pressure chemical vapor deposition.
Zhong discloses in [0060] forming silicon dioxide layers of different thicknesses by modifying parameters of a PECVD process. The first gate dielectric layer of SiO2 is formed using a low-power PECVD process and the second gate dielectric layer of SiO2 is formed using a high-power PECVD process.
Sugahara discloses in Fig. 1 a method of forming two silicon dioxide layers 61 and 63 on each other in a trench where the layers 61 and 63 can have different thicknesses and formed using different processes, see [0025]. Sugahara further discloses in [0040] that the second silicon dioxide layer 63 can be formed of a high temperature oxide deposited by LPCVD.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to form a silicon dioxide as a high temperature oxide deposited using LPCVD such that it can have a different thickness than the lower silicon dioxide layer instead of using the PECVD method of Zhong; if this leads to the anticipated success, in the instant case a gate dielectric that provides the desired amount of electrical isolation for the transistor, it is likely the product not of innovation but of ordinary skill.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Tan in view of Zhong as applied to claim 15 above, and further in view of Leng et al (CN 115083901 and Leng hereinafter; a machine translation is used as an English language equivalent).
Although the method disclosed by Nakano in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 11 above), it fails to expressly disclose:
wherein the first gate dielectric layer is deposited by atomic layer deposition.
Zhong discloses in [0060] forming the first gate dielectric of silicon dioxide formed by a PECVD process.
Leng discloses in [0060] that a gate dielectric of silicon dioxide can be formed using a CVD or ALD process.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to form a silicon dioxide using ALD of Leng instead of using the PECVD method of Zhong; if this leads to the anticipated success, in the instant case a gate dielectric that provides the desired amount of electrical isolation for the transistor, it is likely the product not of innovation but of ordinary skill.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/ Primary Examiner, Art Unit 2813
1/7/2026