DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendments filed 5/13/2026 and 6/17/2026 in which claims 1, 6-8, 15, and 18 were amended, claims 21-26 were added, and claims 2, 4, 5, 12, 13, and 17 were cancelled in 5/13/2026 and claims 21-26 were amended.
Claims 1, 3, 6-11, 14-16, and 18-26 are pending and presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8, 10, 11, 16, 18-20, and 23-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 recites in lines 15-16 that “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer”. The disclosure as originally filed in Fig. 5 teaches that the gate dielectric layer 34 is positioned between the gate conductor layer 36 and the gate dielectric layer 32. Mapping the claims to the disclosure as originally filed, the gate dielectric layer 34 is the first gate dielectric layer and the gate dielectric layer 32 is the second gate dielectric layer.
As to claim 8: Claim 8 recites that “the second gate dielectric layer is thicker than the first dielectric layer.” Claim 6 recites that the second gate dielectric layer is “disposed between the conductor layer and the first gate dielectric layer”, which places the second gate dielectric layer in a different position than what is claimed previously in claim 1 (see paragraph 7 below for the 35 U.S.C. 112(b) rejection of claim 6). Examiner interprets that claim 6 should be consistent with claim 1 and therefore the positioning of the three layers is such that the first gate dielectric layer is between the gate conductor layer and the second gate dielectric layer. Paragraph [0030] of the disclosure states that the gate dielectric layer 34 (the claimed first gate dielectric layer) is thicker than the gate dielectric layer 32 (the claimed second gate dielectric layer). Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer being thicker than the first dielectric layer when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. In view of the 35 U.S.C. 112(b) rejection of claim 6 (see paragraph 7 below), Examiner interprets the claim to be –the first gate dielectric layer is thicker than the second gate dielectric layer–. Appropriate correction is required.
As to claim 10: Claim 10 recites that “the first gate dielectric layer comprises aluminum oxide, and the second gate dielectric layer comprises silicon dioxide.” Claim 6 recites that the second gate dielectric layer is “disposed between the conductor layer and the first gate dielectric layer”, which places the second gate dielectric layer in a different position than what is claimed previously in claim 1 (see paragraph 7 below for the 35 U.S.C. 112(b) rejection of claim 6). Examiner interprets that claim 6 should be consistent with claim 1 and therefore the positioning of the three layers is such that the first gate dielectric layer is between the gate conductor layer and the second gate dielectric layer. Paragraph [0024] of the disclosure teaches that the gate dielectric layer 32 (the claimed second gate dielectric layer) can be aluminum oxide and paragraph [0029] teaches that the gate dielectric layer 34 (the claimed first gate dielectric layer) can be silicon dioxide. Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer being silicon dioxide when the first gate dielectric layer is aluminum oxide when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. In view of the 35 U.S.C. 112(b) rejection of claim 6 (see paragraph 7 below), Examiner interprets the claim to be – the first gate dielectric layer comprises silicon dioxide, and the second gate dielectric layer comprises aluminum oxide–. Appropriate correction is required.
As to claim 11: Claim 11 recites that “the first gate dielectric layer has a thickness in a range of 2.5 nanometers to 10 nanometers.” Claim 6 recites that the second gate dielectric layer is “disposed between the conductor layer and the first gate dielectric layer”, which places the second gate dielectric layer in a different position than what is claimed previously in claim 1 (see paragraph 7 below for the 35 U.S.C. 112(b) rejection of claim 6). Examiner interprets that claim 6 should be consistent with claim 1 and therefore the positioning of the three layers is such that the first gate dielectric layer is between the gate conductor layer and the second gate dielectric layer. Paragraph [0027] of the disclosure teaches that the gate dielectric layer 32 (the claimed second gate dielectric layer) can have a thickness of 2.5 nm to 10 nm. Therefore, the disclosure as originally filed does not provide support for the first gate dielectric layer to have the claimed thickness when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. In view of the 35 U.S.C. 112(b) rejection of claim 6 (see paragraph 7 below), Examiner interprets the claim to be –the second gate dielectric layer has a thickness in a range of 2.5 nanometers to 10 nanometers–. Appropriate correction is required.
As to claim 16: Claim 16 recites “the first gate dielectric layer is deposited at a substrate temperature in a range between 25°C and 400°C.” Paragraph [0024] of the disclosure teaches that the gate dielectric layer 32 (the claimed second gate dielectric layer) may be deposited at a substrate temperature in a range between 25°C and 400°C. Therefore, the disclosure as originally filed does not provide support for the first gate dielectric layer to be deposited at a substrate temperature in the claimed range when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the second gate dielectric layer is deposited at a substrate temperature in a range between 25°C and 400°C–. Appropriate correction is required.
As to claim 18: Claim 18 recites that the second gate dielectric is formed by “depositing a high temperature oxide by low pressure chemical vapor deposition.” Paragraph [0029] of the disclosure teaches that the gate dielectric layer 34 (the claimed first gate dielectric) may be a high temperature oxide deposited by low pressure chemical vapor deposition. Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer to be a high temperature oxide deposited by low pressure chemical vapor deposition when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –wherein forming the first gate dielectric layer disposed on the sidewalls of the trench comprises: depositing –a high temperature oxide deposited by low pressure chemical vapor deposition–. Appropriate correction is required.
As to claim 19: Claim 19 recites that “the second gate dielectric layer is formed at a higher substrate temperature than the first gate dielectric layer.” Paragraph [0029] of the disclosure teaches that the gate dielectric layer 34 (the claimed first gate dielectric) may be deposited at a higher substrate temperature than the gate dielectric layer 32 (the claimed second gate dielectric). Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer to be formed at a higher substrate temperature than the first gate dielectric layer when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the first gate dielectric layer is formed at a higher substrate temperature than the second gate dielectric layer–. Appropriate correction is required.
As to claim 20: Claim 20 recites that “the first gate dielectric layer is deposited by atomic layer deposition.” Paragraph [0024] of the disclosure teaches that the gate dielectric layer 32 (the claimed second gate dielectric) may be deposited by atomic layer deposition. Therefore, the disclosure as originally filed does not provide support for the first gate dielectric layer to be deposited by atomic layer deposition when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the second gate dielectric is deposited by atomic layer deposition–. Appropriate correction is required.
As to claim 23: Claim 23 recites that “the silicon dioxide of the first gate dielectric layer has a higher density than the silicon dioxide of the second gate dielectric layer.” Paragraph [0037] of the disclosure teaches that the silicon dioxide of the gate dielectric layer 32 (the claimed second gate dielectric) may have a higher density than the silicon dioxide of the gate dielectric layer 34 (the claimed first gate dielectric). Therefore, the disclosure as originally filed does not provide support for the silicon dioxide of the first gate dielectric layer to have a higher density than the silicon dioxide of the second gate dielectric layer when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the silicon dioxide of the second gate dielectric layer has a higher density than the silicon dioxide of the first gate dielectric layer–. Appropriate correction is required.
As to claim 24: Claim 24 recites that “the second gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the second gate dielectric layer is thicker than the first gate dielectric layer.” Paragraph [0030] of the disclosure teaches that the gate dielectric layer 34 (the claimed first gate dielectric) may have a thickness in a range between 10 nm and 50 and that the gate dielectric layer 34 (the claimed first gate dielectric) may be thicker than the gate dielectric layer 32 (the claimed second gate dielectric). Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer having a thickness within the claimed range and where the second gate dielectric layer is thicker than the first gate dielectric layer when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the first gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the first gate dielectric layer is thicker than the second gate dielectric layer–. Appropriate correction is required.
As to claim 25: Claim 25 recites that “the second gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the second gate dielectric layer is thicker than the first gate dielectric layer.” Paragraph [0030] of the disclosure teaches that the gate dielectric layer 34 (the claimed first gate dielectric) may have a thickness in a range between 10 nm and 50 and that the gate dielectric layer 34 (the claimed first gate dielectric) may be thicker than the gate dielectric layer 32 (the claimed second gate dielectric). Therefore, the disclosure as originally filed does not provide support for the second gate dielectric layer having a thickness within the claimed range and where the second gate dielectric layer is thicker than the first gate dielectric layer when “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer” as required by claim 1. Examiner believes that in the claim the first and second gate dielectric have been switched for one another. To be consistent with the disclosure as filed, examiner interprets the claim to be –the first gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the first gate dielectric layer is thicker than the second gate dielectric layer–. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites “the second gate dielectric is disposed between the conductor layer and the first gate dielectric layer.” First, there is insufficient antecedent basis for “the conductor layer” in the claim. Claim 1 recites “a gate conductor layer” and no other conductor layer is claimed; therefore, Examiner interprets “the conductor layer” in claim 6 to be –the gate conductor layer–. Second, claim 1 recites in lines 15-16 that “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer”. Claim 6 recites that the second gate dielectric layer is in a different position than what is claimed previously in claim 1. Therefore, it is unclear from claim 6 where the second gate dielectric layer should be relative to the first gate dielectric layer and the gate conductor layer. Examiner interprets that claim 6 should be consistent with claim 1 and therefore the positioning of the three layers is such that the first gate dielectric layer is between the gate conductor layer and the second gate dielectric layer. Claims 7-10 inherit the deficiencies of claim 6. Appropriate correction is required.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 recites in line 1 that it depends from claim 17. However, claim 17 has been cancelled. It is unclear what the dependency of claim 19 should be. Examiner interprets that claim 19 should depend from claim 16. Appropriate correction is required.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 26 recites “the second gate dielectric is disposed between the gate electrode and the first gate dielectric layer.” First, there is insufficient antecedent basis for “the gate electrode” in the claim. Claim 1 recites “a gate conductor layer” and “an electrode”; as claim 26 recites “gate electrode”, Examiner interprets “the gate electrode” in claim 26 to be –the gate conductor layer–. Second, claim 1 recites in lines 15-16 that “the first gate dielectric layer is disposed between the gate conductor layer and the second gate dielectric layer”. Claim 26 recites that the second gate dielectric layer is in a different position than what is claimed previously in claim 1. Therefore, it is unclear from claim 26 where the second gate dielectric layer should be relative to the first gate dielectric layer and the gate conductor layer. Examiner interprets that claim 26 should be consistent with claim 1 and therefore the positioning of the three layers are such that the first gate dielectric layer is between the gate conductor layer and the second gate dielectric layer. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 6-9, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Cai (US 2020/0343370 and Cai hereinafter) in view of Tan et al (US 2017/0316935 and Tan hereinafter).
As to claims 1, 3, 6-9, 21, and 22: Cai discloses [claim 1] a method of forming a structure for a field-effect transistor (Figs. 1-2J; 100; [0011]), the method comprising: forming a doped region (Fig. 1; 109; [0013]) in a semiconductor substrate (comprising 120, 101, 110, 109, and 108; [0011]-[0013]), wherein the semiconductor substrate (comprising 120, 101, 110, 109, and 108) comprises a wide bandgap semiconductor material (semiconductor material can be silicon carbide (SiC); [0008]); forming a trench (Fig. 1; 103; [0012]) including a plurality of sidewalls (left and right sidewall of 103) extending from a top surface (top of 109) of the semiconductor substrate (comprising 120, 101, 110, 109, and 108) into the semiconductor substrate (comprising 120, 101, 110, 109, and 108); forming a first gate dielectric layer (Fig. 1; portion of 115 adjacent to 105; [0012]) on the sidewalls of the trench (103); forming a second gate dielectric layer (Fig. 1; claim doesn’t establish a material difference between the first and second gate dielectric layers so Examiner interprets them to be the same material, such as the material of 115, and the second gate dielectric layer is the portion of 115 adjacent to 108 and 109; [0012]) disposed on the sidewalls of the trench (103); forming a gate conductor layer (Fig. 1; 105; [0012]) inside the trench (103); forming a dielectric layer (Fig. 1; 111; [0013]) including a first portion (111 that is directly over 105) on the gate conductor layer (105) and a second portion (111 that is directly over the top surface of 109) on the top surface (top of 109) of the semiconductor substrate (comprising 120, 101, 110, 109, and 108); and forming an electrode (Fig. 1; 122 is the source electrode; [0014]) coupled (through 112; [0014]) to the doped region (109), wherein the first gate dielectric layer (portion of 115 adjacent to 105) is disposed between the gate conductor layer (105) and the second gate dielectric layer (portion of 115 adjacent to 108 and 109), the first portion (111 that is directly over 105) of the dielectric layer (111) is thicker (111 that is directly over 105 extends from the bottom surface of 122 to the top of 105 that is recessed relative to the top of 109 which is thicker than 111 that is directly over the top of 109 that extends from the bottom surface of 122 to the top of 109) than the second portion (111 that is directly over the top surface of 109) of the dielectric layer (111), and the first portion (111 that is directly over 105) of the dielectric layer (111) is disposed between the gate conductor layer (105) and the electrode (122); [claim 3] wherein the wide bandgap semiconductor material comprises silicon carbide (semiconductor material can be silicon carbide (SiC); [0008]); [claim 6] wherein the second gate dielectric layer (Examiner note: see paragraph 7 above for discussion on how this claim is interpreted; portion of 115 adjacent to 108 and 109) is disposed between the conductor layer (105) and the first gate dielectric layer (portion of 115 adjacent to 105); [claim 7] wherein the first gate dielectric layer (portion of 115 adjacent to 105) and the second gate dielectric layer (portion of 115 adjacent to 108 and 109) are disposed between the gate conductor layer (105) and the sidewalls of the trench (103); [claim 8] wherein the second gate dielectric layer (Examiner note: see sub-paragraph a above for discussion on how this claim is interpreted; portion of 115 adjacent to 108 and 109) is thicker (first gate dielectric portion can be interpreted to be thicker than the second gate dielectric portion as they comprise the same material of layer 115 in Cai) than the first gate dielectric layer (portion of 115 adjacent to 105); [claim 9] wherein the first gate dielectric layer (portion of 115 adjacent to 105) comprises silicon dioxide (115 can be silicon dioxide; [0020]), and the second gate dielectric layer (portion of 115 adjacent to 108 and 109) comprises silicon dioxide (115 can be silicon dioxide; [0020]).
Cai fails to expressly disclose [claim 1] cleaning the semiconductor substrate at the sidewalls of the trench with atomic layer etching; after cleaning the semiconductor substrate at the sidewalls of the trench with atomic layer etching, forming the first gate dielectric layer on the sidewalls of the trench; [claim 21] wherein cleaning the semiconductor substrate at the sidewalls of the trench with the atomic layer etching comprises: removing a portion of the semiconductor material of the semiconductor substrate with the atomic layer etching; [claim 22] wherein cleaning the semiconductor substrate at the sidewalls of the trench with atomic layer etching comprises: removing a monolayer of the semiconductor material of the semiconductor substrate.
Tan discloses in [0045] that atomic layer etching can be used on substrates that comprise semiconductor materials (such as silicon carbide) which have trenches formed therein.
Tan discloses [claim 1] cleaning the semiconductor substrate (Figs. 1 and 5; substrate; [0045]) at the sidewalls of the trench (surface of the substrate is modified/cleaned, the surface can include a trench) with atomic layer etching (Figs. 1 and 2; [0043]-[0047]); after cleaning the semiconductor substrate at sidewalls of the trench with atomic layer etching, forming the first gate dielectric layer on the sidewalls of the trench (the process of Tan can be applied to a trench after it is provided and before layers are formed thereon; [0036]-[0040] and [0056]); [claim 21] wherein cleaning the semiconductor substrate at the sidewalls of the trench with the atomic layer etching comprises: removing a portion of the semiconductor material of the semiconductor substrate with the atomic layer etching (Fig. 2; a monolayer or two can be removed of the substrate material when the feature is cleaned using ALE; [0052]-[0053]); [claim 22] wherein cleaning the semiconductor substrate at the sidewalls of the trench with atomic layer etching comprises: removing a monolayer of the semiconductor material of the semiconductor substrate (Fig. 2; a monolayer or two can be removed of the substrate material when the feature is cleaned using ALE; [0052]-[0053]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to apply the method of cleaning a surface that comprises carbon, such as a trench in a silicon carbide substrate, by removing a monolayer of the substrate material of Tan to the method of Cai prior to forming insulating layers in the trench in the SiC substrate in order to provide a trench sidewall surface that is smooth and clean ([0040], [0045], and [0051]).
Claims 10, 11, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan as applied to claims 1 and 6 above, and further in view of Sato et al (US 2019/0148546 and Sato hereinafter).
As to claims 10, 11, 25, and 26: Although the structure disclosed by Cai in view of Tan shows substantial features of the claimed invention (discussed in paragraph 14 above), it fails to expressly disclose:
[claim 10] wherein the first gate dielectric layer comprises aluminum oxide, and the second gate dielectric layer comprises silicon dioxide; [claim 11] wherein the first gate dielectric layer has a first thickness in a range of 2.5 nanometers to 10 nanometers; [claim 25] wherein the second gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the second gate dielectric layer is thicker than the first gate dielectric layer; [claim 26] wherein the second gate dielectric layer is disposed between the gate electrode and the first gate dielectric layer.
Cai combined with Tan discloses a MOSFET structure having an oxide 115 as a gate dielectric.
Examiner note: see paragraph 7 above for discussion on how these claims are interpreted.
Sato discloses a MOSFET structure in Fig. 1 [claim 10] wherein the first gate dielectric layer (GA) comprises aluminum oxide (aluminum oxide; [0053] and [0101]), and the second gate dielectric layer (GO2) comprises silicon dioxide (SiO2; [0053] and [0102]); [claim 11] wherein the first gate dielectric layer (GA) has a first thickness in a range of 2.5 nanometers to 10 nanometers (7-10 nm; [0053]).
Sato discloses a MOSFET structure in Fig. 1 and [0053] that the gate dielectric GI1a can comprise just GA and GO2 and that the first gate dielectric GA can have a thickness from 7-10 nm and the second gate dielectric GO2 can have a thickness from 5-20 nm. It is also well known that the thickness of the gate dielectric affects the electrical isolation and threshold voltage of the transistor and is thus a result effective variable.
Therefore, Sato discloses a range for the second gate dielectric GO2 that has values (specifically 11-20 nm) higher than the highest value for the first gate dielectric GA (10 nm).
Hence, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the gate dielectric such that it comprises a bi-layer of aluminum oxide and silicon dioxide as taught by Sato instead of just silicon dioxide as in Cai; if this leads to the anticipated success, in the instant case a gate dielectric structure that isolates the gate electrode from the semiconductor substrate, it is likely the product not of innovation but of ordinary skill.
Further, a person having ordinary skill in the art before the effective filing date of the claimed invention to choose a value for the second gate dielectric that is larger than that of the first gate dielectric as Sato discloses values that are expressly greater for the second gate dielectric compared to the first gate dielectric and one of ordinary skill would be motivated optimize the thicknesses of the respective gate dielectric layers to arrive at the claimed thickness relationship while balancing a need to provide a transistor with a desired threshold voltage.
In addition, Sato discloses a range for the second gate dielectric GO2 that has values (specifically 11-20 nm) higher than the highest value for the first gate dielectric GA (10 nm) and that thickness range of GO2 is within/overlaps with the claimed range.
As stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.”
Thus, a person having ordinary skill in the art before the effective filing date of the claimed invention to choose a value for the second gate dielectric that is larger than that of the first gate dielectric and falls within the claimed range as Sato discloses values that are expressly greater for the second gate dielectric (and fall within the claimed range) compared to the first gate dielectric and one of ordinary skill would be motivated optimize the thicknesses of the respective gate dielectric layers to arrive at the claimed thickness relationship while balancing a need to provide a transistor with a desired threshold voltage.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the gate dielectric such that it comprises a bi-layer of aluminum oxide and silicon dioxide as taught by Sato instead of just silicon dioxide as in Cai in view of Tan; if this leads to the anticipated success, in the instant case a gate dielectric structure that isolates the gate electrode from the semiconductor substrate, it is likely the product not of innovation but of ordinary skill.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan as applied to claim 1 above, and further in view of Tsuji et al (US 2024/0079275 and Tsuji hereinafter).
Although the method disclosed by Cai in view of Tan shows substantial features of the claimed invention (discussed in paragraph 14 above), it fails to expressly disclose:
further comprising: annealing the first gate dielectric layer in an ambient including nitrous oxide.
Cai combined with Tan teaches a gate dielectric 115 that comprises SiO2, which is formed by a thermal oxidation process ([0020]).
Tsuji discloses in [0046] that a first SiO2 film formed on the surface of a trench sidewall in a SiC substrate can be annealed in a nitrous oxide atmosphere after it is formed and before the next gate dielectric layer is formed.
Therefore, given the teachings of Tsuji, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Cai in view of Tan by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Tsuji, by employing an annealing step in a nitrous oxide atmosphere after forming a silicon dioxide film through thermal oxidation of a SiC trench sidewall surface in order to provide a transistor with a passivated surface between the silicon dioxide and the substrate ([0046]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan as applied to claim 1 above, and further in view of Zhong (CN 109585564 and Zhong hereinafter; a machine translation is used as an English language equivalent and was mailed 2/13/2026).
Although the method disclosed by Cai in view of Tan shows substantial features of the claimed invention (discussed in paragraph 14 above), it fails to expressly disclose:
wherein forming the first gate dielectric layer on the surface of the semiconductor substrate comprises: depositing the first gate dielectric layer on the surface of the semiconductor substrate.
Zhong discloses a SiC based transistor wherein forming the first gate dielectric layer (low-power deposited SiO2; [0058]-[0062]) on the surface of the semiconductor substrate (SiC) comprises: depositing (through PECVD; [0059]) the first gate dielectric layer (low-power deposited SiO2) on the semiconductor substrate (SiC) at the sidewalls of the trench (4).
Therefore, given the teachings of Zhong, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Cai in view of Tan by employing the well-known or conventional features of SiC transistor fabrication, such as displayed by Zhong, by employing a gate dielectric that comprises silicon dioxide formed by using different parameters of a PECVD process to obtain different thicknesses, where the first gate silicon dioxide layer has a thickness within the claimed range, in order to provide a transistor with reduced on-resistance, improved channel mobility, and enhanced reliability ([0072]).
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan in view of Zhong as applied to claim 15 above, and further in view of Yang et al (CN 113555287 and Yang hereinafter; a machine translation is used as an English language equivalent and was mailed 2/13/2026).
As to claims 16 and 19: Although the method disclosed by Cai in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 18 above), it fails to expressly disclose:
[claim 16] wherein the first gate dielectric layer is deposited at a substrate temperature in a range between 25°C and 400°C; [claim 19] wherein the second gate dielectric layer is formed at a higher substrate temperature than the first gate dielectric layer.
Examiner note: see paragraph 7 above for discussion on how these claims are interpreted.
Zhong discloses in [0060] forming silicon dioxide layers of different thicknesses by modifying parameters of a PECVD process. The first gate dielectric layer of SiO2 is formed using a low-power PECVD process and the second gate dielectric layer of SiO2 is formed using a high-power PECVD process.
Yang discloses in [0100] that a SiO2 film formed using a power of 50W and a temperature of 150°C produces a film with thickness of 170 nm. Yang discloses in [0134] that a SiO2 film formed using a power of 100W and a temperature of 250°C produces a film of 250 nm. Therefore, Yang discloses conditions where a thinner first SiO2 film is deposited at a lower temperature and lower power than the thicker second SiO2 film formed using a higher power.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to adjust the PECVD parameters to form the SiO2 films, as indicated by Zhong, with different thicknesses by adjusting the power and temperature such that the first gate dielectric is formed using a lower temperature than the second gate dielectric using a temperature that is within the claimed range in order to yield the gate dielectric of sufficient thickness and quality to provide desired electrical isolation for the transistor.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan in view of Zhong as applied to claim 15 above, and further in view of Sugahara (JP 2018200919 and Sugahara hereinafter; a machine translation is used as an English language equivalent and was mailed 2/13/2026).
Although the method disclosed by Cai in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 18 above), it fails to expressly disclose:
wherein forming the second gate dielectric layer on the first gate dielectric layer comprises: depositing a high temperature oxide by low pressure chemical vapor deposition.
Examiner note: see paragraph 7 above for discussion on how this claim is interpreted.
Zhong discloses in [0060] forming silicon dioxide layers of different thicknesses by modifying parameters of a PECVD process. The first gate dielectric layer of SiO2 is formed using a low-power PECVD process and the second gate dielectric layer of SiO2 is formed using a high-power PECVD process.
Sugahara discloses in Fig. 1 a method of forming two silicon dioxide layers 61 and 63 on each other in a trench where the layers 61 and 63 can have different thicknesses and formed using different processes, see [0025]. Sugahara further discloses in [0040] that the second silicon dioxide layer 63 can be formed of a high temperature oxide deposited by LPCVD.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to form a silicon dioxide as a high temperature oxide deposited using LPCVD such that it can have a different thickness than the lower silicon dioxide layer instead of using the PECVD method of Zhong; if this leads to the anticipated success, in the instant case a gate dielectric that provides the desired amount of electrical isolation for the transistor, it is likely the product not of innovation but of ordinary skill.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan in view of Zhong as applied to claim 15 above, and further in view of Leng et al (CN 115083901 and Leng hereinafter; a machine translation is used as an English language equivalent and was mailed 2/13/2026).
Although the method disclosed by Cai in view of Tan in view of Zhong shows substantial features of the claimed invention (discussed in paragraph 18 above), it fails to expressly disclose:
wherein the first gate dielectric layer is deposited by atomic layer deposition.
Zhong discloses in [0060] forming the first gate dielectric of silicon dioxide formed by a PECVD process.
Leng discloses in [0060] that a gate dielectric of silicon dioxide can be formed using a CVD or ALD process.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to form a silicon dioxide using ALD of Leng instead of using the PECVD method of Zhong; if this leads to the anticipated success, in the instant case a gate dielectric that provides the desired amount of electrical isolation for the transistor, it is likely the product not of innovation but of ordinary skill.
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan as applied to claim 9 above, and further in view of Sugahara.
As to claims 23 and 24: Although the method disclosed by Cai in view of Tan shows substantial features of the claimed invention (discussed in paragraph 14 above), it fails to expressly disclose:
[claim 23] wherein the silicon dioxide of the first gate dielectric layer has a higher density than the silicon dioxide of the second gate dielectric layer; [claim 24] wherein the second gate dielectric layer has a second thickness in a range of 10 nanometers to 50 nanometers, and the second gate dielectric layer is thicker than the first gate dielectric layer.
Examiner note: see paragraph 7 above for discussion on how these claims are interpreted.
Sugahara discloses in Fig. 1 a method of forming two silicon dioxide layers 61 and 62 (spin on glass that is silica glass is a silicon dioxide layer) on each other in a trench where the layers 61 and 62 can have different thicknesses and are formed using different processes, see [00240, [0026], and [0028]. Sugahara further discloses in [0028] that the first silicon dioxide layer 61 can have a higher density than the second silicon dioxide layer 62, where the first silicon dioxide layer 61 (the claimed second gate dielectric layer in claim 1) is between the substrate and the second silicon dioxide layer 62 (the claimed first gate dielectric layer in claim 1). Sugahara also discloses in [0029] that the second silicon dioxide layer 62 has a thickness of 80 nm to 730 nm at its thickest point in the center of the trench and that it becomes thinner with increasing distance from the center, which implies that there will be thicknesses that overlap with the claimed thickness of 10 nm to 50 nm as one gets further from the center of the trench. Fig. 1 of Sugahara and [0025] and [0029] disclose that the first silicon dioxide layer 61 is thinner than the second silicon dioxide layer 62.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing to form a silicon dioxide as a SOG that is formed on a lower silicon dioxide layer formed by another method (e.g. CVD or thermal oxidation) such that the SOG (the second silicon dioxide layer) has a lower density and is thicker than the first silicon dioxide layer; if this leads to the anticipated success, in the instant case a gate dielectric that provides the desired amount of electrical isolation for the transistor, it is likely the product not of innovation but of ordinary skill.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Tan in view of Sato as applied to claim 11 above, and further in view of Sato et al (US 2019/0148546 and Sato hereinafter).
Although the structure disclosed by Cai in view of Tan in view of Sugahara shows substantial features of the claimed invention (discussed in paragraph 23 above), it fails to expressly disclose:
Examiner note: see paragraph 7 above for discussion on how this claim is interpreted.
Cai combined with Tan and Sugahara discloses a MOSFET structure having an oxide 115 as a gate dielectric.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, 6-11, 14-16, and 18-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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