DETAILED ACTION
The present application, filed on (8/3/2023), is being examined under the first inventor to file provisions of the AIA . Claims (1-14) are pending and being examined.
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Drawing of Fig 3 is not consistent with that of Fig 5B since the potential difference in 5B is disclosed to be 3kV while from Fig 3 it should be 13 kV absolute. This needs to be corrected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Koichi Nagami (US 20160240353).
Regarding claims 1-2 and 14 Koichi Nagami discloses a plasma processing apparatus (Fig 2) comprising:
a chamber (10);
a substrate support disposed in the chamber (12);
a bias electrode disposed in the substrate support (12);
a DC voltage source electrically connected to the bias electrode and configured to apply a pulsed DC voltage to the bias electrode (Fig 2 DA); and
a controller (84) configured to perform a first process to calculate a potential difference between a wafer disposed on the substrate support and the bias electrode (Para 10).
Regarding this limitation, Koichi Nagami does not explicitly teach a threshold but teaches that a large potential difference between the substrate and susceptor could be a source of abnormal discharge (Para 11) and should be reduced. To determine that the difference is large, comparison to a threshold would therefore have been obvious before the filing date of the application. This teaches the second process of claim 1 and determination of potential difference in claim 14.
Regarding claim 14, application of DC through (DA) would be applicable to both first and second periods of Pulse voltage application.
Koichi Nagami further disclose the third process of adjusting a parameter of pulse modulated DC (DA) to reduce potential difference (Abstract, Para 2, 33-36).
Koichi Nagami discloses reducing potential difference for all the values of modulated DC and therefore discloses that for low level of pulsed DC.
Regarding claims 3, voltage shift would occur due to the application of voltage from the application unit (Para 13).
Regarding claims 4-5 modulation adjusts the duty cycle to reduce potential difference (Para 61-62).
Regarding claims 6-7 modulation adjusts the amplitude of the applied voltage to reduce potential difference (Par 39).
Regarding claims 8-9 modulation adjusts the pulse frequency since it applies pulsed signal of the applied voltage to reduce potential difference (Fig 6).
Regarding claims 10-13 low pass filter is disclosed (140 and para 82).
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of non-statutory double patenting as being unpatentable over claims of U.S. Patent No.11776795. Although the claims at issue are not identical, they are not patentably distinct from each other because patented claims 1 and 12 disclose detection of substrate potential, calculation of difference and reduction by using DC voltage to shift the potential or use, duty cycle, amplitude or frequency of applied pulse DC.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cho et al (US 20170352567) disclose application of DC to reduce potential difference between workpiece and the substrate holding plate (Fig 3 and Para 31, 33-34).
Chiang et al (US 20070065594) discloses application of negative bias to substrate holder electrode with a variable duty cycle to modulate wafer potential (Para 54).
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RAM N. KACKAR
Primary Examiner
Art Unit 1716
/RAM N KACKAR/Primary Examiner, Art Unit 1716