DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/04/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because a part is marked twice (i.e., markings overlap, see 110 of fig. 2b). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1-12 are objected to because of the following informalities: phrase "structure of pixel layout" should either read "structure of a pixel layout" or "pixel layout structure". Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama et al. (US Publication 20210384280) in view of Lee et al. (US Publication 20190005886).
Regarding independent claims 1 and 7, Akiyama teaches a structure of pixel layout (fig. 4), being used in a pixel unit (fig. 1, 102)/an electroluminescent display (fig. 1, 101), wherein the electroluminescent display comprises a plurality of pixel units (102) arranged in an array, and at least one pixel unit comprises a structure of pixel layout (fig. 4),
the structure of pixel layout comprises:
a transition area (see figure below), provided with a second type of well contact (fig. 4, 406), the second type of well contact is coupled to a first voltage terminal (paragraph 0048, “n-type well layer 406 is electrically connected to the power supply voltage Vdd”), and electrically provided with a capacitor (205 and 206);
a high-voltage device area (see figure below), located on a side within the pixel unit, electrically provided with a first type of high-voltage transistor (204) and an electroluminescent device (120), the first type of high-voltage transistor and the capacitor share the second type of well contact (fig. 4, 204, 205, and 206 share indirect contact with 406), the electroluminescent device is coupled to the first type of high-voltage transistor (fig. 4) and a second voltage terminal (paragraph 0053, “the anode 451 rendered conductive with the source region (diffusion region 415) of the reset transistor 204 is set to the power supply voltage Vss”), respectively, wherein one of the first voltage terminal and the second voltage terminal has a highest driving voltage, and the other one has a lowest driving voltage (paragraph 0038, “power supply potential Vdd is, for example, +10 V based on the power supply potential Vss”); and
a low-voltage device area (see figure below), located on a side within the pixel unit away from the high-voltage device area, the transition area is located between the high-voltage device area and the low-voltage device area (see figure below), the low-voltage device area is electrically provided with a second type of low-voltage transistor (203), and the second type of low-voltage transistor comprises a first type of well
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contact (408 and 410).
Akiyama does not teach coupled to an intermediate voltage terminal, wherein the intermediate voltage terminal is used to provide an intermediate voltage, and the intermediate voltage is between the highest driving voltage and the lowest driving voltage.
Lee teaches coupled to an intermediate voltage terminal (fig. 3C, VMM), wherein the intermediate voltage terminal is used to provide an intermediate voltage, and the intermediate voltage is between the highest driving voltage and the lowest driving voltage (paragraph 0061, “intermediate-potential power voltage terminal VMM supplies a voltage having a level between the voltage supplied by the high-potential power voltage terminal VDD and the voltage supplied by the low-potential power voltage terminal VSS”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of pixel layout/the electroluminescent display of Akiyama and the intermediate voltage of Lee in order to reduce inrush current (Lee paragraph 0065).
Regarding dependent claims 2 and 8, Akiyama further teaches the structure of pixel layout according to claim 1/the electroluminescent display according to claim 7,
wherein the low-voltage device area is further electrically provided with a first type of low-voltage transistor (fig. 4, 202), the first type of low-voltage transistor, the capacitor and the first type of high-voltage transistor share the second type of well contact (fig. 4, 202, 205, 206, and 204 share indirect contact with 406).
Claims 3-4 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Lee as applied to claims 1 and 7 above respectively, and further in view of Son et al. (US Publication 20150037955).
Regarding dependent claims 3 and 9, Akiyama in view of Lee teaches the structure of pixel layout according to claim 1/the electroluminescent display according to claim 8.
Akiyama in view of Lee does not teach [wherein the structure of pixel layout] further comprises an insulating layer, extending from the high-voltage device area to the low-voltage device area, with a first thickness in the high-voltage device area, a second thickness in the low-voltage device area, and a thickness gradient in the transition area, the first thickness is greater than the second thickness, and the thickness gradient decreases from a side of the high-voltage device area towards a side of the low-voltage device area.
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Son teaches [wherein the structure of pixel layout] further comprises an insulating layer (fig. 13, 162), extending from the high-voltage device area to the low-voltage device area (see figure below), with a first thickness in the high-voltage device area (see figure below), a second thickness in the low-voltage device area (see figure below), and a thickness gradient (see figure below) in the transition area, the first thickness is greater than the second thickness (see figure below), and the thickness gradient decreases from a side of the high-voltage device area towards a side of the low-voltage device area (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of pixel layout/electroluminescent display of Akiyama in view of Lee and the insulating layer of Son in order to compensate for a subthreshold slope decrease (Son paragraph 0019).
Regarding dependent claims 4 and 10, Son further teaches the structure of pixel layout according to claim 3/the electroluminescent display according to claim 9,
wherein the capacitor is located on a side of the thickness gradient close to the high-voltage device area, a side of the thickness gradient close to the low-voltage device area, or on the thickness gradient (see marked figure above, capacitor of Akiyama can be rearranged to be placed on the thickness gradient per MPEP 2144.04).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of pixel layout/the electroluminescent display of Akiyama in view of Lee and the placing of the capacitor on the insulating layer of Son per the reason(s) stated above in claims 3 and 9.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Lee as applied to claims 1 and 7 above respectively, and further in view of Ishimaru et al. (US Publication 20210035491).
Regarding dependent claims 5 and 11, Akiyama in view of Lee teaches the structure of pixel layout according to claim 1/the electroluminescent display according to claim 7.
Akiyama in view of Lee does not teach [wherein the structure of pixel layout] further comprises a first type of substrate, the first type of substrate has a second type of well provided therein, the second type of well encompasses the high-voltage device area, the transition area and a part of the low-voltage device area, and the second type of well contact is located in the second type of well.
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Ishimaru teaches further comprises a first type of substrate (fig. 6, 90), the first type of substrate has a second type of well (NWC, NWA, and NWB) provided therein, the second type of well encompasses the high-voltage device area, the transition area and a part of the low-voltage device area (see figure below), and the second type of well contact is located in the second type of well (fig. 6, RNA located in NWA).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of pixel layout/ the electroluminescent display of Akiyama in view of Lee and the second type of well of Ishimaru in order to suppress power loss (Ishimaru paragraph 0059).
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Lee as applied to claims 1 and 7 above respectively, and further in view of Peng et al. (US Publication 20210225268).
Regarding dependent claims 6 and 12, Akiyama further teaches the structure of pixel layout according to claim 1/the electroluminescent display according to claim 7,
wherein the structure of pixel layout has a first boundary (see figure below, b1) and a second boundary (see figure below, b2) in a length direction, and there is a first predetermined distance between the first boundary and the second boundary (see figure below, d1); and
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the structure of pixel layout has a third boundary (see figure below, b3) and a fourth boundary (see figure below, b4) in a width direction, and there is a second predetermined distance between the third boundary and the fourth boundary (see figure below, d2), wherein the high-voltage device area is configured as being towards the second boundary along the first boundary, and the low-voltage device area is configured as being towards the first boundary along the second boundary (see figure below).
Akiyama in view of Son does not teach the first predetermined distance and the second predetermined distance are not greater than 10 microns.
Peng teaches the first predetermined distance and the second predetermined distance are not greater than 10 microns (paragraph 0061, “an individual light emitting pixel, whether R, G, or B can have a nominal side dimensions of 2.5-5.0 microns width, although the pixels can be smaller (1.0 microns wide as a non-limiting example) or larger”, length of pixel can be adjusted to fit limitations per MPEP 2144.05).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of pixel layout/the electroluminescent display of Akiyama in view of Lee and the first and second predetermined distances of in order to increase apparent light efficiency to a viewer (Peng paragraph 0061).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897