Attorney’s Docket Number: 22RO0050US01/50649-01923
Filing Date: 8/04/2023
Claimed Foreign Priority Date: 8/19/2022 (FR2208404)
Inventors: Julien et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the election filed 12/19/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of invention I, reading on a transistor, in the reply filed on 12/19/2025, is acknowledged. The applicant cancelled claims 13-18, added claim 19, and indicated that claims 1-12 and 19 read on the elected invention. The examiner agrees.
Claim Interpretation
Claim 11 recites the line “An electronic device comprising at least one transistor according to claim 1”, which will be interpreted as “The transistor according to claim 1, wherein the transistor is comprised within an electronic device”.
Claim 12 recites the line “A radio frequency switch comprising at least one transistor according to claim 1”, which will be interpreted as “The transistor according to claim 1, wherein the transistor is comprised within a radio frequency switch”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 1 recites the limitation “semiconductor” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purposes of furthering examination, “semiconductor” will be construed as reciting “semiconductor layer”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, and 10-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tokranov (US 20240047555 A1).
Regarding claim 1, Tokranov (see, e.g., fig. 1A) shows all aspects of the instant invention including a transistor (e.g., FET 1.1A) comprising:
A semiconductor layer (e.g., semiconductor body 110);
A stack (e.g., stack of gate dielectric 124 + gate conductor 125) on the semiconductor layer (e.g., semiconductor body 110) comprising a gate insulator (e.g., gate dielectric layer 124) and a gate region (e.g., gate conductor 125) on the gate insulator (e.g., 26.sub.1. portion gate dielectric layer 124, see annotated fig. 1);
Wherein the gate region (e.g., gate conductor 125) comprises a first portion (e.g., upper gate portion included in L3 length) and a second portion (e.g., lower gate portion included in L1 length) between the first portion (e.g., upper gate portion included in L3 length) and the gate insulator (e.g., 26.sub.1. portion gate dielectric layer 124);
Wherein the first portion (e.g., upper gate portion included in L3 length) of the gate region (e.g., gate conductor 125) has a first length (e.g., length of upper gate portion) in a first lateral direction (e.g., horizontal direction) of the transistor (e.g., FET 1.1A);
Wherein the second portion (e.g., lower gate portion included in L1 length) of the gate region (e.g., gate conductor 125) has a second length (e.g., length of lower gate portion) in the first lateral direction (e.g., horizontal direction) shorter (see, e.g., paragraph 36) than the first length (e.g., length of upper gate portion).
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Annotated Fig. 1
Regarding claim 2, Tokranov (see, e.g., fig. 1A) shows a source region (e.g., left-side source/drain region 122) and a drain region (e.g., right-side source/drain region 122) in a body region (e.g., 1.1A side of semiconductor body 110) of the semiconductor layer (e.g., semiconductor body 110), wherein an upper portion (e.g., upper portion of 1.1A side of semiconductor body 110) of the body region (e.g., 1.1A side of semiconductor body 110, see paragraph 29), between the source region (e.g., left-side source/drain region 122) and the drain region (e.g., right-side source/drain region 122), forms a channel region (e.g., channel region 123) of the transistor (e.g., FET 1.1A), wherein the first lateral direction (e.g., horizontal direction) is parallel (e.g., note that channel also extends in horizontal direction, so parallel to first lateral direction) to a length direction (e.g., horizontal direction) of the channel region (e.g., channel region 123), said length direction (e.g., horizontal direction) extending between the source region (e.g., left-side source/drain region 122) and the drain region (e.g., right-side source/drain region 122), and wherein the gate region (e.g., gate conductor 125) extends over the channel region (e.g., channel region 123) of the body region (e.g., 1.1A side of semiconductor body 110).
Regarding claim 3, Tokranov (see, e.g., fig. 1A) shows a lightly-doped drain region (e.g., left-side source/drain extension region 121 + right-side source/drain extension region 121 + paragraph 29 “The source/drain extension region(s) can have the second type conductivity at a relatively low conductivity level”) between the channel region (e.g., channel region 123) and each source (e.g., left-side source/drain region 122) and drain region (e.g., right-side source/drain region 122).
Regarding claim 4, Tokranov (see, e.g., fig. 1A) shows wherein the second portion (e.g., lower gate portion included in L1 length) is centered in the first lateral direction (e.g., horizontal direction) with respect to the first portion (e.g., upper gate portion included in L3 length).
Regarding claim 5, Tokranov (see, e.g., fig. 1A) shows wherein the gate insulator (e.g., 26.sub.1. portion gate dielectric layer 124) comprises a first region (e.g., central portion of 26.sub.1. gate dielectric layer 124) having a first thickness at a central area of the gate region (e.g., gate conductor 125), and a second region (e.g., lateral edge portion of 26.sub.1. gate dielectric 124) having a second thickness, greater than the first thickness (e.g., note that the gate dielectric layer 124 expands upward, which increases the thickness at the lateral portion, see annotated fig. 2 below), at lateral edges of the second portion (e.g., lower gate portion included in L1 length) of the gate region (e.g., gate conductor 125).
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Annotated Fig. 2
Regarding claim 6, an oxide layer (e.g., 26.sub.2 portion of gate dielectric layer 124 + paragraph 34 “The gate dielectric layer 124 can include a high-K gate dielectric layer…Illustrative high-K dielectric materials include, but are not limited to, hafnium (HO-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide…”) coating sides of the first (e.g., upper gate portion included in L3 length) and second portions (e.g., lower gate portion included in L1 length) of the gate region (e.g., gate conductor 125), and an insulating spacer (e.g., gate sidewall spacer 115A) in contact with the oxide layer (e.g., 26.sub.2 portion of gate dielectric layer 124 + paragraph 34 “The gate dielectric layer 124 can include a high-K gate dielectric layer…Illustrative high-K dielectric materials include, but are not limited to, hafnium (HO-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide…”).
Regarding claim 10, Tokranov (see, e.g., fig. 1A) shows wherein a distance, in the first lateral direction (e.g., horizontal direction), between lateral edges of the first portion (e.g., upper gate portion included in L3 length) and lateral edges of the second portion (e.g., lower gate portion included in L1 length) is in a range from 1 to 30 nm, for example, from 1 to 20 nm, or even from 1 to 10 nm (see, e.g., paragraphs 37-38 “…L2…may also be approximately equal to the length L3 of the gate structure…L1 could be 1, 2, 3 or more nm less…”).
Regarding claim 11, Tokranov (see, e.g., fig. 1A) shows wherein the transistor (e.g., FET 1.1A) is comprised within an electronic device (e.g., semiconductor structure 100.1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tokranov in view of Hoentschel (US 20160126146 A1).
Regarding claim 7, Tokranov (see, e.g., fig. 1A) fails to show wherein the oxide layer comprises a layer of reoxidation having a thickness greater than or equal to 5 nm and positioned on and covering the side of the first portion of the gate region.
Hoentschel (see, e.g., fig. 1A), in a similar device to Tokranov, teaches wherein an oxide layer (e.g., reoxidized SiO.sub.2 layer 119”) comprises a layer of reoxidation (see, e.g., paragraph 22”) having a thickness greater than or equal to 5 nm (see, e.g., paragraph 22 “…thickness of 3 nm to 6 nm”) and positioned on and covering a first portion of a gate region (e.g., poly-Si 10).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the reoxidation configuration of Hoentschel within the oxide layer of Tokranov, in order to achieve the expected result of protecting the gate structure from oxidation and contamination during the manufacturing process, while still providing electrical isolation as necessary, and also limiting the thickness of the layer to reduce the cost during the manufacturing of the device while still maintaining a uniform dielectric around the gate structure.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tokranov in view of Xie (US 10388747 B1).
Regarding claim 8, Tokranov (see, e.g., fig. 1A) fails to show wherein a cavity in the gate region defined by the side of the second portion between the first portion and the gate insulator is filled with an insulating material of low dielectric constant.
Xie (see, e.g., fig. 6), in a similar device to Tokranov, teaches a cavity (e.g., spacers 112) in the gate region (e.g., replacement gate structure 119) defined by the side of a second portion (e.g., lower, thin portion of gate structure 119) between a first portion (e.g., upper, thicker portion of gate structure 119) and a gate insulator (e.g., layer of insulating material 113) is filled with an insulating material of low dielectric constant (see, e.g., paragraph 16 “…112 may be…a low-k material”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the low-k dielectric material of Xie between the first portion and the gate insulator of Tokranov, in order to achieve the expected result of reducing potential capacitive coupling within the device, and providing additional dielectric capabilities as necessary.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tokranov in view of Yin (US 20150102416 A1).
Regarding claim 9, Tokranov (see, e.g., fig. 1A) shows wherein the first portion (e.g., upper gate portion included in L3 length) of the gate region (e.g., gate conductor 125) comprises polysilicon (see, e.g., paragraph 34 “…gate conductor layer 125 can include one or more work function (WF) metal or metal alloy layers….WF metal alloy layers…optional conductive fill material layer can be, for example, doped polysilicon…”).
Tokranov (see, e.g., fig. 1A), however, fails to show wherein the second portion of the gate region comprises a polycrystalline silicon-germanium alloy.
Yin (see, e.g., fig. 3h), in a similar device to Tokranov, teaches a gate region (e.g., first gate 520a) comprising a polycrystalline silicon-germanium alloy (see, e.g., paragraph 103 “…polycrystalline silicon-germanium…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polycrystalline silicon-germanium of Yin within the second portion of the gate region of Tokranov, in order to improve the tunable characteristics of the gate structure through a reduced bandgap, increasing the device’s current capability.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tokranov in view of Hurwitz (US 20180069035 A1).
Regarding claim 12, Tokranov (see, e.g., fig. 1A) fails to explicitly show the transistor is comprised within a radio frequency switch.
Hurwitz (see, e.g., fig. 1), in a similar device to Tokranov, teaches a radio frequency switch (e.g., RF transmitter switch 120) comprising a transistor (e.g., FETs 110).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the RF configuration of Hurwitz to comprise the transistor of Tokranov, in order to achieve the expected result of providing RF functionalities using the transistor setup.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tokranov in view of Reznicek (US 20210083139 A1).
Regarding claim 19, Tokranov (see, e.g., fig. 1A) shows an oxide layer (e.g., 26.sub.2 portion of gate dielectric layer 124 + paragraph 34 “The gate dielectric layer 124 can include a high-K gate dielectric layer…Illustrative high-K dielectric materials include, but are not limited to, hafnium (HO-based dielectrics (e.g., hafnium oxide, hafnium silicon oxide…”) coating sides of the first (e.g., upper gate portion included in L3 length) and second portions (e.g., lower gate portion included in L1 length) of the gate region (e.g., gate conductor 125).
Tokranov (see, e.g., fig. 1A), however, fails to show wherein the oxide layer has a thickness greater than or equal to 5 nm.
Reznicek (see, e.g., fig. 9), in a similar device to Tokranov, teaches wherein an oxide layer (e.g., gate dielectric material layer 20L + paragraph 66 “…gate dielectric material layer 20L can be composed of…HfO.sub.2, ZrO.sub.2, La.sub.2O.sub3…”) can comprise a thickness greater than or equal to 5 nm (see, e.g., paragraph 67 “…the gate dielectric material layer 20L can have a thickness in a range from 1 nm to 10 nm”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness range of Reznicek within the oxide layer of Tokranov, in order to limit the cost of fabrication during the manufacturing of the device while still maintaining a uniform dielectric around the gate structure.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814