DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10, in the reply filed on 1/6/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2014/0346458).
Regarding claim 1, Park discloses a display device (paragraph 0008) comprising:
a substrate (10, figs. 1-5 and paragraph 0056);
a semiconductor layer disposed on the substrate (212, 312, fig. 2 and paragraphs 0059, 0074);
a gate insulating layer disposed on the semiconductor layer (13, fig. 3 and paragraph 0060);
a gate layer comprising a first layer disposed on the gate insulating layer and
including a first metal, and a second layer disposed on the first layer and including a
second metal (114, 214, 314, 115, 215, 315, fig. 4 and paragraphs 0091-0092), wherein a first through hole is defined through the second layer in a
direction perpendicular to an upper surface of the first layer (fig. 6 and paragraph 0098); and an interlayer insulating layer disposed on the gate layer (16, fig. 4 and paragraph 0061).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2020/0395428).
Regarding claim 1, Baek discloses a display device comprising:
a substrate (100, fig. 7A and paragraph 0099);
a semiconductor layer disposed on the substrate (221, fig. 7A and paragraph 0101);
an insulating layer disposed on the semiconductor layer (130, fig. 7A and paragraph 0107);
a stacked metal layer (1400, fig. 7B and paragraph 0109) comprising a first layer disposed on the insulating layer (multilayer 1404, 1403, 1402, fig. 7B and paragraphs 0109-0110) and including a first metal, and a second layer disposed on the first layer and including a second metal (1401, fig. 7B and paragraphs 0109-0110), wherein a first through hole is defined through the second layer in a
direction perpendicular to an upper surface of the first layer (401H, fig. 7E and paragraph 0127); and
an interlayer insulating layer disposed on the stacked metal layer (OL, fig. 7E and paragraph 0123).
Baek does not disclose wherein the stacked metal layer is a gate layer. Baek’s stacked metal layer is for source/drain electrodes and pads for electrical communication (430, 440, 400, fig. 7E and paragraph 0116). However, it would have been obvious to one of ordinary skill in the art at the time of filing to utilize Baek’s stacked metal layer for gate layer electrodes, since gate electrodes and source/drain electrodes and pads are all used for electrical communications to operate transistor based devices and therefore have functional equivalence.
Regarding claim 2, Baek further discloses wherein an acute angle between a first side surface of the pad 400 (fig. 7D and paragraph 0122). Baek does not explicitly disclose wherein the acute angle between a first layer and an upper surface of the substrate is less than an acute angle between a second side surface of the second layer and the upper surface of the substrate, wherein the first side surface and the second side surface correspond to a same side surface of the gate layer. However, such variance of the angle can be attributed to the variance of the etching rates of the different metal layers of Baek’s stack and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 3, Baek further discloses wherein the first through hole (401H, fig. 7F) is defined through the interlayer insulating layer (OL, fig. 7F) and the second layer together (401, fig. 7F), and
the display device further comprises a first conductive layer disposed on the
interlayer insulating layer and connected to the first layer through the first through hole (510, fig. 7E and paragraph 0126).
Regarding claim 4, Baek further discloses wherein a groove is defined in the first layer to correspond to the first through hole, and the first conductive layer fills the groove (510, fig. 7E).
Regarding claim 5, Baek further discloses wherein an angle between the first side surface and the second side surface is less than about 180° (fig. 7D and paragraph 0122).
Regarding claim 6, Baek further discloses wherein the first conductive layer is
connected to the semiconductor layer through a second through hole defined through the interlayer insulating layer and the insulating layer (430, 440 source/drain connections to semiconductor layer 221, fig. 7D).
Regarding claim 7, Baek further discloses wherein
the substrate comprises a first area (PA, fig. 7G), in which the pad is located, and a
second area (DA, fig. 7G), in which the semiconductor layer is located, among areas other than the first area, the first through hole (401H, fig. 7G) is located in the first area, and the second through hole is located in the second area (510, pixel electrode connection, fig. 7G).
Regarding claim 8, Baek further discloses wherein
the first metal includes titanium (Ti) (paragraph 0070), and
the second metal includes aluminum (Al) (paragraph 0070).
Regarding claim 9, Baek further discloses wherein an etch rate of the first metal is lower than an etch rate of the second metal under a same condition (inherent properties of metal layers disclosed in paragraph 0070).
Regarding claim 10, Baek further discloses wherein the upper surface of the first layer (top of 402, fig. 7G) is in direct contact with the first conductive layer through the first through hole (910, fig. 7G and paragraph 0141).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2006/0091396 discloses a display panel substrate with tapered gate electrodes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 2/21/26