DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 6-20 in the reply filed on 11/24/2025 is acknowledged. Non-elected claims 1-5 have been canceled. Claims 6-25 are examined on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et.al., U.S. Pat. Pub. 2021/0242135, hereafter Chen.
Regarding claim 13, Chen discloses (Figs 3A, 3B)
a method of forming a wafer-to-wafer bonded structure, further comprising:
placing (Fig. 3A, Fig. 1, step [102]) a first wafer [300] comprising first electrical circuits [320] in proximity to a second wafer [200] comprising second electrical circuits [250] such that first bond pad structures [322] of the first wafer [300] are approximately aligned with second bond pad structures [220] of the second wafer [200]; and
determining (Fig. 1, step 104, Fig. 3B) a position of one or more first alignment marks [FM] of the first wafer [300] relative to one or more second alignment marks [230] of the second wafer [200] by imaging one or more first alignment marks and the second alignment marks through a first dielectric window structure [330] formed in the first wafer [300].
Regarding claim 14, Chen further discloses (Figs 3A-3D, Figs 4A, 4B) wherein imaging the one or more first alignment marks and the second alignment marks through the first dielectric window structure further comprises:
directing visible light through the first dielectric window structure; and
observing or recording an image of the one or more first alignment marks and the second alignment marks generated by visible light (Figs 4A,4B show visually the alignment process)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et.al., U.S. Pat. Pub. 2021/0242135, hereafter Chen, in view of Lin et. al., U. S. Pat. Pub. 2021/0375781, hereafter Lin.
Regarding claim 15, Chen discloses everything as applied above. Chen further discloses further comprising (Fig. 1, steps [106]-[110], Fig. 3B):
adjusting a relative position of the first wafer [300] and the second wafer [200] to align the one or more first alignment marks [FM] of the first wafer [300] relative to the second alignment marks [230] of the second wafer [200] based on imaging of the one or more first alignment marks and the second alignment marks through the first dielectric window structure [330];
placing (Fig. 3C) the first wafer [300] in contact with the second wafer [200] such that the first bond pad structures [322] of the first wafer are contacting the second bond pad structures [220] of the second wafer [200].
Chen fails to explicitly disclose performing a direct bonding process to bond the first wafer to the second wafer
However, Lin discloses (par. [0067]) performing a direct bonding process to bond the first wafer to the second wafer.
It would have been obvious to one of ordinary skill in the art to use direct bonding for stacking and aligning semiconductor wafers, such as those of Lin, because hybrid bonding is both more secure and scales better than convention BGA as critical dimension gets smaller.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et.al., U.S. Pat. Pub. 2021/0242135, hereafter Chen, in view of Examiner’s Official Notice.
Regarding claim 16, Chen discloses everything as applied above. Chen fails to explicitly disclose wherein placing the first wafer in proximity to the second wafer further comprises placing the first wafer and the second wafer in a face-to-back configuration, wherein:
the first bond pad structures of the first wafer are back-side bond pad structures formed on a back side of a substrate of the first wafer; and
the second bond pad structures of the second wafer are front-side bond pad structures formed on a front side of the second wafer such that the front-side bond pad structures are electrically connected to electrical interconnect structures of the second wafer
However, the Examiner takes an Official Notice that both back-side bond pad structures and front-side bond pad structures are well known in the semiconductor arts, and staking wafers front-side to back-side is well known.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to stack wafers front-side to back-side, as disclosed by Examiner’s Official Notice, to produce 3D-IC package and reduce package size.
Regarding claim 17, Chen discloses everything as applied above. Chen fails to explicitly disclose
wherein placing the first wafer in proximity to the second wafer further comprises placing the first wafer and the second wafer in a face-to-face configuration, and wherein:
the first bond pad structures of the first wafer comprise first front-side bond pad structures formed on the first wafer; and
the second bond pad structures of the second wafer are second front-side bond pad structures formed on the second wafer.
However, the Examiner takes an Official Notice that bond pads can be formed on both front side and back side of wafers, and stacking first and second wafers in a face-to-face configuration to produce 3D IC circuit would be obvious, since such a stacking reduces package size.
Allowable Subject Matter
Claims 6-12 and 21-25 are allowed. Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art of record fails to explicitly disclose or make obvious the step of
removing a back-side portion of the substrate to reveal the first dielectric window structure.
Claims 7-12 are claims dependent on claim 6 and contain all of its limitations.
Regarding claim 18, the prior art of record fails to explicitly disclose or make obvious the step of
determining a position of one or more third alignment marks of the third wafer relative to one or more fourth alignment marks of the first wafer by imaging the one or more third alignment marks and the one or more fourth alignment marks through a second dielectric window structure formed in the third wafer.
Claims 19-20 are objected to because they depend on claim 18.
Regarding claim 21, the prior art of record fails to explicitly disclose or make obvious a second dielectric window structure and aligning through the second dielectric window.
Claims 22-25 are allowable because they contain all limitations of the independent claim 21
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Uchiyama et. al., U.S. Pat. 12,564,067, shows (Fig. 5B) aligning and stacking wafers by viewing alignment marks [509], [519] through a dielectric window [529]. However, Uchiyama is silent about hybrid bonding or alignment of pads on the wafers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893