DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 3/19/2026 in which claims 1, 3, 11, 13, 18, and 19 were amended.
Claims 1-20 are pending with claim 7 remaining withdrawn and claims 1-6 and 8-20 presented for examination.
Claim Objections
Claim 4 is objected to because of the following informalities: in line 4, "a gate dielectric layer" should be amended to read -the gate dielectric . Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 2018/0212062 and Xie hereinafter) in view of Song (US 2009/0068801 and Song hereinafter) in view of Shin et al (US 2008/0303020 and Shin hereinafter).
As to claims 1, 3-5, and 10: Xie discloses [claim 1] a method of forming a transistor (Figs. 2A-2I; [0057]), comprising: depositing a gate dielectric blanket layer (Fig. 2C; 31; [0075]) on a substrate (1; [0075]); depositing a semiconductor material blanket layer (Fig. 2D; not shown but an amorphous IGZO layer (the blanket layer) is formed and then processed using lithography to form the shown patterned layer 4; [0076]-[0077]) on the gate dielectric blanket layer (31); forming a photoresist pattern (Fig. 2D; not shown but the photoresist is detailed in [0077]; [0077]) on the semiconductor blanket layer (not shown but is formed and then patterned to provide the shown layer 4); etching the semiconductor material blanket layer (Fig. 2D; not shown but discussed in [0077]; [0076]-[0077]) using the photoresist pattern (photoresist) as a mask to form a semiconductor layer (4; [0076]-[0077]); depositing a second dielectric layer (Fig. 2H; 6; [0081]) on the semiconductor layer (4); [claim 3] further comprising forming a word line (Fig. 2B; 21; [0074]) and source and drain electrodes (Fig. 2I; 81 and 82, respectively; [0083]) where the source and drain electrodes are formed in one of the first and second dielectric layers (6; [0083]); [claim 4] further comprising: forming a trench (Fig. 2A; 11; [0073]) in the substrate (1); forming a word line (Fig. 2B; 21; [0074]) in the trench (11); and forming a gate dielectric layer (Fig. 2D; 31; [0075]) between the word line (21) and the semiconductor layer (4); [claim 5] further comprising: forming first and second via cavities (Fig. 2H; 71 and 72, respectively; [0081]) in the second dielectric layer (6), the first via cavity (71) exposing the source region (51; [0081]) and the second via cavity (72) exposing the drain region (52; [0081]); and forming a source electrode (Fig. 2I; 81; [0083]) in the first via cavity (71) and a drain electrode (82; [0083]) in the second via cavity (72); [claim 10] where the semiconductor layer (4) comprises a metal oxide semiconductor material (IGZO is a metal oxide semiconductor material; [0076]).
Xie fails to expressly disclose [claim 1] depositing a first dielectric layer on a substrate; where the gate dielectric blanket and the semiconductor material blanket layer are formed on the first dielectric layer; etching the gate dielectric blanket layer and the semiconductor material blanket layer using the photoresist pattern to form the semiconductor layer and a gate dielectric layer by exposing the first dielectric layer; [claim 3] where the word line and source and drain electrodes are formed in different ones of the first and second dielectric layers; [claim 10] wherein: the first dielectric layer comprises silicon dioxide.
Xie discloses forming a TFT that has a bottom gate for use in LCD technology ([0002]).
Song discloses a TFT with a bottom gate in a LCD device ([0001] and [0059]) comprising [claim 1] depositing a first dielectric layer on a substrate (Fig. 1; 1 is described as a substrate by Song and is a glass or plastic material, which are dielectric materials; as the claim does not materially distinguish the first dielectric layer from the substrate, Examiner interprets that they can be the same material such that the upper portion of 1 is the claimed first dielectric layer and the lower portion of 1 is the substrate as the upper portion will be formed on the lower portion; [0041]); where the gate dielectric blanket (Fig. 5; 5; [0044]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]) are formed on the first dielectric layer (upper portion of 1); etching the gate dielectric blanket layer (Figs. 6 and 7; 5; [0044]-[0045]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]-[0045]) using the photoresist pattern (41; [0044]) to form the semiconductor layer (6 and 7 in Fig. 7; [0045]) and a gate dielectric layer (5 in Fig. 7; [0045]) by exposing the first dielectric layer (upper portion of 1); [claim 10] wherein: the first dielectric layer comprises silicon dioxide (the layer 1 comprises glass, of which silicon dioxide is a major component; 41).
As to [claim 3] where the word line and source and drain electrodes are formed in different ones of the first and second dielectric layers and [claim 4] where the trench is formed in the first dielectric layer, when the substrate 1 of Xie is modified by the material of Song such that the material of 1 is a first dielectric material and the upper portion of 1 is the first dielectric material and the lower portion of 1 is the substrate, the trench 11 and word line 21 of Xie will be in the first dielectric layer (as shown in Fig. 2B of Xie) and the source and drain electrodes 81 and 82 will be formed in the second dielectric layer 6 (as shown in Fig. 2I).
Xie discloses that the method of forming a TFT is to be used in an LCD device. Song discloses that in LCD devices with a TFT, the gate insulating blanket layer will be patterned so as to be confined to the area around the bottom gate of the TFT.
Therefore, given the teachings of Song, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie by employing the well-known or conventional features of LCD device fabrication, such as displayed by Song, by employing an etching step that etches the blanket gate insulating layer and the semiconductor material blanket layer using a single photoresist in order to expose the pixel electrode in the LCD such that it can be electrically contacted in a later step ([0045]) using a process that uses fewer photoresist materials thus reducing costs and time ([0049]).
Xie in view of Song fail to expressly disclose [claim 1] forming a hydrogen diffusion barrier film on a channel region of the semiconductor layer; where the second dielectric layer is formed also on the hydrogen diffusion barrier film; and performing a thermal annealing process to diffuse hydrogen into the semiconductor layer to form a source region and a drain region on opposing sides of the channel region.
Shin discloses a bottom gate TFT in which the method includes [claim 1] forming a hydrogen diffusion barrier film (Fig. 2B; 15; [0032]) on a channel region (14a; [0032]) of the semiconductor layer (14; [0031]); where the second dielectric layer (Fig. 2C; 16; [0040]) is formed also on the hydrogen diffusion barrier film (15); and performing a thermal annealing process (Fig. 2C; thermal treatment; [0041]) to diffuse hydrogen (hydrogen atoms 16a; [0041]) into the semiconductor layer (14) to form a source region (14b; [0041]) and a drain region (14c; [0041]) on opposing sides of the channel region (14a).
Given the teachings of Shin, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie in view of Song by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin, by employing a hydrogen blocking layer over a channel layer and performing an anneal to diffuse hydrogen into the source and drain areas of a semiconductor layer in order to reduce the resistivity of the source and drain regions ([0041]).
As to [claim 10] wherein the second dielectric layer comprises silicon dioxide or silicon nitride, Xie discloses in [0064] that the second dielectric layer 6 can comprise SiOx.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing SiO2 from the finite list of well-known SiOx materials that are used in semiconductor technology; if this leads to the anticipated success, in the instant case a material that can provide electrical isolation between adjacent components, it is likely the product not of innovation but of ordinary skill.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin as applied to claim 1 above, and further in view of Tsukamoto et al (JP H0555521 and Tsukamoto hereinafter; a machine translation is used as an English language equivalent).
Xie in view of Song in view of Shin discloses wherein the performing the thermal annealing process comprises heating the substrate at a temperature ranging from about 100 °C to about 300 °C (Fig. 2C; thermal treatment at 300°C; [0041]).
Xie in view of Song in view of Shin fail to expressly disclose where the thermal annealing process to introduce hydrogen into a lower layer from a silicon nitride layer is performed in a hydrogen (H2) containing atmosphere.
Tsukamoto discloses introducing hydrogen into a lower layer from a silicon nitride layer and an ambient atmosphere is performed in a hydrogen (H2) containing atmosphere (hydrogenation in a hydrogen atmosphere; [0025])
Given the teachings of Shin in view of Tsukamoto, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie in view of Song by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin in view of Tsukamoto, by employing a hydrogenation process in a hydrogen atmosphere whereby hydrogen from a silicon nitride and from the ambient atmosphere of hydrogen into a semiconductor layer at a temperature within the claimed range in order to introduce a large amount of hydrogen from the silicon nitride layer and the ambient hydrogen atmosphere to significantly reduce the resistivity and trap density of the source and drain regions of the active layer ([0025]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin as applied to claim 5 above, and further in view of Kim et al (US 2014/0139772 and Kim hereinafter).
Although the method disclosed by Xie in view of Song in view of Shin shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
wherein: the first and second via cavities expose opposing sides of the hydrogen diffusion barrier film; and the source and drain electrodes respectively contact the opposing sides of the hydrogen diffusion barrier film and vertically overlap opposing portions of the word line.
Kim discloses a bottom gate TFT structure in Fig. 6 wherein: the first and second via cavities (openings in which 12 and 13 are formed; [0040]) expose opposing sides of the hydrogen diffusion barrier film (120f; [0089]); and the source and drain electrodes (12 and 13; [0040]) respectively contact the opposing sides of the hydrogen diffusion barrier film (120f) and vertically overlap opposing portions of the word line (11; [0040]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to form the source/drain electrodes of a width great enough to contact the sidewalls of the hydrogen barrier layer over the channel region of the semiconductor layer and overlapping the gate electrode/word line to provide a greater contact area between the source/drain electrodes and the source/drain regions.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin as applied to claim 1 above, and further in view of Park et al (US 2022/0208806 and Park hereinafter).
As to claims 8 and 9: Although the method disclosed by Xie in view of Song in view of Shin shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
[claim 8] wherein the hydrogen diffusion barrier film comprises a dielectric material and has a thickness ranging from about 1nm to about 200nm; [claim 9] wherein the hydrogen diffusion barrier film comprises Al2O3.
Park discloses TFTs with hydrogen barrier layers [claim 8] wherein the hydrogen diffusion barrier film (hydrogen diffusion barrier film; [0026]) comprises a dielectric material (aluminum oxide; [0026]) and has a thickness ranging from about 1nm to about 200nm (60 nm; [0093]); [claim 9] wherein the hydrogen diffusion barrier film comprises Al2O3 (aluminum oxide; [0026]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the hydrogen diffusion barrier layer to be aluminum oxide with a thickness of 60 nm from the list of Park; if this leads to the anticipated success, in the instant case a layer of sufficient thickness to prevent hydrogen from diffusing into a channel region of a semiconductor layer, it is likely the product not of innovation but of ordinary skill.
Claims 11, 13, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin in view of Oshima (US 2019/0115476 and Oshima hereinafter).
As to claims 11, 13, 14, and 17: Xie discloses [claim 11] a method of forming a transistor (Figs. 2A-2I; [0057]), comprising: depositing a gate dielectric blanket layer (Fig. 2C; 31; [0075]) on a substrate (1; [0075]); depositing a semiconductor material blanket layer (Fig. 2D; not shown but an amorphous IGZO layer (the blanket layer) is formed and then processed using lithography to form the shown patterned layer 4; [0076]-[0077]) on the gate dielectric blanket layer (31); forming a photoresist pattern (Fig. 2D; not shown but the photoresist is detailed in [0077]; [0077]) on the semiconductor blanket layer (not shown but is formed and then patterned to provide the shown layer 4); etching the semiconductor material blanket layer (Fig. 2D; not shown but discussed in [0077]; [0076]-[0077]) using the photoresist pattern (photoresist) as a mask to form a semiconductor layer (4; [0076]-[0077]); depositing a second dielectric layer (Fig. 2H; 6; [0081]) on the semiconductor layer (4); [claim 13] further comprising forming a word line (Fig. 2B; 21; [0074]); [claim 17] where the semiconductor layer (4) comprises a metal oxide semiconductor material (IGZO is a metal oxide semiconductor material; [0076]).
Xie fails to expressly disclose [claim 11] depositing a first dielectric layer on a substrate; where the gate dielectric blanket and the semiconductor material blanket layer are formed on the first dielectric layer; etching the gate dielectric blanket layer and the semiconductor material blanket layer using the photoresist pattern to form the semiconductor layer and a gate dielectric layer, by exposing the first dielectric layer; [claim 13] where the word is formed in the first dielectric layer, wherein the gate dielectric layer is disposed between the semiconductor layer and the word line; [claim 17] wherein: the first dielectric layer comprises silicon dioxide.
Xie discloses forming a TFT that has a bottom gate for use in LCD technology ([0002]).
Song discloses a TFT with a bottom gate in a LCD device ([0001] and [0059]) comprising [claim 11] depositing a first dielectric layer on a substrate (Fig. 1; 1 is described as a substrate by Song and is a glass or plastic material, which are dielectric materials; as the claim does not materially distinguish the first dielectric layer from the substrate, Examiner interprets that they can be the same material such that the upper portion of 1 is the claimed first dielectric layer and the lower portion of 1 is the substrate as the upper portion will be formed on the lower portion; [0041]); where the gate dielectric blanket (Fig. 5; 5; [0044]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]) are formed on the first dielectric layer (upper portion of 1); etching the gate dielectric blanket layer (Figs. 6 and 7; 5; [0044]-[0045]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]-[0045]) using the photoresist pattern (41; [0044]) to form the semiconductor layer (6 and 7 in Fig. 7; [0045]) and a gate dielectric layer (5 in Fig. 7; [0045]), by exposing the first dielectric layer (upper portion of 1); [claim 13] wherein the gate dielectric layer (Fig. 7; 5) is disposed between the semiconductor layer (comprising 6 and 7) and the word line (31; [0041]); [claim 17] wherein: the first dielectric layer comprises silicon dioxide (the layer 1 comprises glass, of which silicon dioxide is a major component; 41).
As to [claim 13] where the word line is formed in the first dielectric layer, when the substrate 1 of Xie is modified by the material of Song such that the material of 1 is a first dielectric material and the upper portion of 1 is the first dielectric material and the lower portion of 1 is the substrate, the trench 11 and word line 21 of Xie will be in the first dielectric layer (as shown in Fig. 2B of Xie).
Xie discloses that the method of forming a TFT is to be used in an LCD device. Song discloses that in LCD devices with a TFT, the gate insulating blanket layer will be patterned so as to be confined to the area around the bottom gate of the TFT.
Therefore, given the teachings of Song, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie by employing the well-known or conventional features of LCD device fabrication, such as displayed by Song, by employing an etching step that etches the blanket gate insulating layer and the semiconductor material blanket layer using a single photoresist in order to expose the pixel electrode in the LCD such that it can be electrically contacted in a later step ([0045]) using a process that uses fewer photoresist materials thus reducing costs and time ([0049]).
Xie in view of Song fail to expressly disclose [claim 11] form a hydrogen diffusion barrier film on the semiconductor layer; where the second dielectric layer is formed also on the hydrogen diffusion barrier film; and diffusing hydrogen into the semiconductor layer to form a source region and a drain region on opposing sides of a channel region; [claim 14] wherein the gate dielectric and the word line are formed prior to performing the thermal annealing process.
Shin discloses a bottom gate TFT in which the method includes [claim 11] form a hydrogen diffusion barrier film (Fig. 2B; 15; [0032]) on the semiconductor layer (14; [0031]); where the second dielectric layer (Fig. 2C; 16; [0040]) is deposited on the hydrogen diffusion barrier film (15); and diffusing hydrogen (Fig. 2C; hydrogen atoms 16a; [0041]) into the semiconductor layer (14) to form a source region (14b; [0041]) and a drain region (14c; [0041]) on opposing sides of a channel region (14a; [0041]); [claim 14] wherein the gate dielectric (Fig. 2A; 13; [0038]) and the word line (12; [0038]) are formed prior to performing the thermal annealing process (Fig. 2C; thermal treatment; [0041]).
Given the teachings of Shin, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie in view of Song by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin, by employing a hydrogen blocking layer over a channel layer and performing an anneal to diffuse hydrogen into the source and drain areas of a semiconductor layer in order to reduce the resistivity of the source and drain regions ([0041]).
Xie in view of Song in view of Shin fail to expressly disclose forming the hydrogen diffusion barrier film by [claim 11] depositing a barrier layer blanket material on the semiconductor layer; patterning the barrier layer blanket material to form the hydrogen diffusion barrier film.
Shin states that the hydrogen diffusion barrier film 15 is formed only on the channel region but not how, see [0032] and [0039].
Oshima discloses in Figs. 3A-5C a method of forming a layer 13 that is desired only on a channel region 12A ([0058]) of a semiconductor layer 12 in a TFT by forming a blanket layer of the material 13M ([0053]) and then patterning the blanket layer of material 13M to form the layer 13 ([0056]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to provide the hydrogen diffusion barrier film 15 of Shin by applying a blanket material of the barrier layer over the semiconductor layer (as done by Oshima with 13M) and then patterning the blanket layer such that the diffusion barrier film 15 in the channel region remains (as done by Oshima to form 13) as the deposition and etching technique was well-known in the art and the application of which would have resulted in the predictable results of controlling the remaining portion of the blanket layer to remain in a desired area.
As to [claim 17] wherein the second dielectric layer comprises silicon dioxide or silicon nitride, Xie discloses in [0064] that the second dielectric layer 6 can comprise SiOx.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing SiO2 from the finite list of well-known SiOx materials that are used in semiconductor technology; if this leads to the anticipated success, in the instant case a material that can provide electrical isolation between adjacent components, it is likely the product not of innovation but of ordinary skill.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin in view of Oshima as applied to claim 11 above, and further in view of Tsukamoto.
Xie in view of Song in view of Shin in view of Oshima discloses wherein the performing the diffusing hydrogen comprises heating the substrate at a temperature ranging from about 100 °C to about 300 °C (Fig. 2C; thermal treatment at 300°C; [0041]).
Xie in view of Song in view of Shin in view of Oshima fail to expressly disclose where the thermal annealing process to introduce hydrogen into a lower layer from, in part, a silicon nitride layer is performed in a hydrogen (H2) containing atmosphere.
Tsukamoto discloses where the thermal annealing process to introduce hydrogen into a lower layer from a silicon nitride layer is performed in a hydrogen (H2) containing atmosphere (hydrogenation in a hydrogen atmosphere; [0025]).
Given the teachings of Shin in view of Oshima in view of Tsukamoto, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie in view of Song by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin in view of Oshima in view of Tsukamoto, by employing a hydrogenation process in a hydrogen atmosphere whereby hydrogen from a silicon nitride and from the ambient atmosphere of hydrogen into a semiconductor layer at a temperature within the claimed range in order to introduce a large amount of hydrogen from the silicon nitride layer and the ambient hydrogen atmosphere to significantly reduce the resistivity and trap density of the source and drain regions of the active layer ([0025]).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin in view of Oshima as applied to claim 11 above, and further in view of Park.
As to claims 15 and 16: Although the method disclosed by Xie in view of Song in view of Shin in view of Oshima shows substantial features of the claimed invention (discussed in paragraph 15 above), it fails to expressly disclose:
[claim 15] wherein the hydrogen diffusion barrier film comprises a dielectric material and has a thickness ranging from about 1nm to about 200nm; [claim 16] wherein the hydrogen diffusion barrier film comprises Al2O3.
Park discloses TFTs with hydrogen barrier layers [claim 15] wherein the hydrogen diffusion barrier film (hydrogen diffusion barrier film; [0026]) comprises a dielectric material (aluminum oxide; [0026]) and has a thickness ranging from about 1nm to about 200nm (60 nm; [0093]); [claim 16] wherein the hydrogen diffusion barrier film comprises Al2O3 (aluminum oxide; [0026]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the hydrogen diffusion barrier layer to be aluminum oxide with a thickness of 60 nm from the list of Park; if this leads to the anticipated success, in the instant case a layer of sufficient thickness to prevent hydrogen from diffusing into a channel region of a semiconductor layer, it is likely the product not of innovation but of ordinary skill.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin in view of Tsukamoto.
As to claims 18 and 19: Xie discloses [claim 18] a method of forming a transistor (Figs. 2A-2I; [0057]), comprising: depositing a gate dielectric blanket layer (Fig. 2C; 31; [0075]) on a substrate (1; [0075]); depositing a semiconductor material blanket layer (Fig. 2D; not shown but an amorphous IGZO layer (the blanket layer) is formed and then processed using lithography to form the shown patterned layer 4; [0076]-[0077]) on the gate dielectric blanket layer (31); forming a photoresist pattern (Fig. 2D; not shown but the photoresist is detailed in [0077]; [0077]) on the semiconductor blanket layer (not shown but is formed and then patterned to provide the shown layer 4); etching the semiconductor material blanket layer (Fig. 2D; not shown but discussed in [0077]; [0076]-[0077]) using the photoresist pattern (photoresist) as a mask to form a semiconductor layer (4; [0076]-[0077]); depositing a second dielectric layer (Fig. 2H; 6; [0081]) on the semiconductor layer (4); [claim 19] further comprising forming a word line (Fig. 2B; 21; [0074]) and source and drain electrodes (Fig. 2I; 81 and 82, respectively; [0083]) where the source and drain electrodes are formed in one of the first and second dielectric layers (6; [0083]).
Xie fails to expressly disclose [claim 18] depositing a first dielectric layer on a substrate; where the gate dielectric blanket and the semiconductor material blanket layer are formed on the first dielectric layer; etching the gate dielectric blanket layer and the semiconductor material blanket layer using the photoresist pattern to form the semiconductor layer and a gate dielectric layer, by exposing the first dielectric layer; [claim 19] where the word line and source and drain electrodes are formed in different ones of the first and second dielectric layers.
Xie discloses forming a TFT that has a bottom gate for use in LCD technology ([0002]).
Song discloses a TFT with a bottom gate in a LCD device ([0001] and [0059]) comprising [claim 18] depositing a first dielectric layer on a substrate (Fig. 1; 1 is described as a substrate by Song and is a glass or plastic material, which are dielectric materials; as the claim does not materially distinguish the first dielectric layer from the substrate, Examiner interprets that they can be the same material such that the upper portion of 1 is the claimed first dielectric layer and the lower portion of 1 is the substrate as the upper portion will be formed on the lower portion; [0041]); where the gate dielectric blanket (Fig. 5; 5; [0044]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]) are formed on the first dielectric layer (upper portion of 1); etching the gate dielectric blanket layer (Figs. 6 and 7; 5; [0044]-[0045]) and the semiconductor material blanket layer (comprising 6 and 7; [0044]-[0045]) using the photoresist pattern (41; [0044]) to form the semiconductor layer (6 and 7 in Fig. 7; [0045]) and a gate dielectric layer (5 in Fig. 7; [0045]), by exposing the first dielectric layer (upper portion of 1).
As to [claim 19] where the word line and source and drain electrodes are formed in different ones of the first and second dielectric layers, when the substrate 1 of Xie is modified by the material of Song such that the material of 1 is a first dielectric material and the upper portion of 1 is the first dielectric material and the lower portion of 1 is the substrate, the trench 11 and word line 21 of Xie will be in the first dielectric layer (as shown in Fig. 2B of Xie) and the source and drain electrodes 81 and 82 will be formed in the second dielectric layer 6 (as shown in Fig. 2I).
Xie discloses that the method of forming a TFT is to be used in an LCD device. Song discloses that in LCD devices with a TFT, the gate insulating blanket layer will be patterned so as to be confined to the area around the bottom gate of the TFT.
Therefore, given the teachings of Song, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie by employing the well-known or conventional features of LCD device fabrication, such as displayed by Song, by employing an etching step that etches the blanket gate insulating layer and the semiconductor material blanket layer using a single photoresist in order to expose the pixel electrode in the LCD such that it can be electrically contacted in a later step ([0045]) using a process that uses fewer photoresist materials thus reducing costs and time ([0049]).
Xie in view of Song fail to expressly disclose [claim 18] forming a hydrogen diffusion barrier film on a channel region of the semiconductor layer; where the second dielectric layer is formed also on the hydrogen diffusion barrier film; and heating the substrate at a temperature ranging from about 100 °C to about 300 °C to form a source region and a drain region on opposing sides of the channel region.
Shin discloses a bottom gate TFT in which the method includes [claim 18] forming a hydrogen diffusion barrier film (Fig. 2B; 15; [0032]) on a channel region (14a; [0032]) of the semiconductor layer (14; [0031]); where the second dielectric layer (Fig. 2C; 16; [0040]) is formed also on the hydrogen diffusion barrier film (15); and heating the substrate at a temperature ranging from about 100 °C to about 300 °C (Fig. 2C; thermal treatment at 300°C; [0041]) to form a source region (14b; [0041]) and a drain region (14c; [0041]) on opposing sides of the channel region (14a).
Given the teachings of Shin, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Xie in view of Song by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin, by employing a hydrogen blocking layer over a channel layer and performing an anneal to diffuse hydrogen into the source and drain areas of a semiconductor layer in order to reduce the resistivity of the source and drain regions ([0041]).
Xie in view of Song in view of Shin fail to expressly disclose where the heating process to form a source and drain region by introducing hydrogen into the semiconductor layer from a silicon nitride layer is performed [claim 18] in a hydrogen (H2) containing atmosphere.
Tsukamoto discloses where the heating process to form a source and drain region by introducing hydrogen into the semiconductor layer from a silicon nitride layer is performed [claim 18] in a hydrogen (H2) containing atmosphere (hydrogenation in a hydrogen atmosphere; [0025]).
Given the teachings of Shin in view of Tsukamoto, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Fukase by employing the well-known or conventional features of TFT fabrication, such as displayed by Shin in view of Tsukamoto, by employing a hydrogenation process in a hydrogen atmosphere whereby hydrogen from a silicon nitride and from the ambient atmosphere of hydrogen into a semiconductor layer at a temperature within the claimed range in order to introduce a large amount of hydrogen from the silicon nitride layer and the ambient hydrogen atmosphere to significantly reduce the resistivity and trap density of the source and drain regions of the active layer ([0025]).
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Song in view of Shin in view of Tsukamoto as applied to claim 18 above, and further in view of Park.
Xie combined with Song, Shin, and Tsukamoto disclose where the semiconductor layer (4) comprises a metal oxide semiconductor material (IGZO is a metal oxide semiconductor material; [0076]).
Xie in view of Song in view of Shin in view of Tsukamoto discloses wherein: the first dielectric layer comprises silicon dioxide (Fig. 1 of Song; the layer 1 comprises glass, of which silicon dioxide is a major component; 41).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a substrate material that comprises SiO2 from the finite list of Song; if this leads to the anticipated success, in the instant case a material that can provide electrical isolation between adjacent components, it is likely the product not of innovation but of ordinary skill.
Xie in view of Song in view of Shin in view of Tsukamoto fail to expressly disclose wherein: the hydrogen diffusion barrier film comprises a dielectric material and has a thickness ranging from about 1nm to about 200nm.
Park discloses TFTs with hydrogen barrier layers wherein: the hydrogen diffusion barrier film (hydrogen diffusion barrier film; [0026]) comprises a dielectric material (aluminum oxide; [0026]) and has a thickness ranging from about 1nm to about 200nm (60 nm; [0093]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the hydrogen diffusion barrier layer to be aluminum oxide with a thickness of 60 nm from the list of Park; if this leads to the anticipated success, in the instant case a layer of sufficient thickness to prevent hydrogen from diffusing into a channel region of a semiconductor layer, it is likely the product not of innovation but of ordinary skill.
As to wherein the second dielectric layer comprises silicon dioxide or silicon nitride, Xie discloses in [0064] that the second dielectric layer 6 can comprise SiOx.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing SiO2 from the finite list of well-known SiOx materials that are used in semiconductor technology; if this leads to the anticipated success, in the instant case a material that can provide electrical isolation between adjacent components, it is likely the product not of innovation but of ordinary skill.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 and 8-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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