DETAILED ACTION
This application, 18/230952, attorney docket 22RO0134US01/50649-01924, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to STMicroelectronics (Rousset) SAS, and claims foreign priority to FR2208512, filed 08/25/2022 Applicant's election without traverse of Group I, claims 1-7 in the reply filed on 12/30/2025 is acknowledged. Claims 8-10 were cancelled by the applicant.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “depositing dielectric layers…to form regions of spacers having a width in a direction perpendicular to the sides of the first gate region;
etching to remove a part of the deposited dielectric layers …so as to reduce a width of the regions of spacers…a first implanting of dopants aligned on the regions of spacers” it is not clear which region of spacers is being implanted.
Claim 2 recites, “wherein depositing dielectric layers comprises first depositing one or more dielectric layers before etching to remove and second depositing one or more dielectric layers after etching to remove; wherein etching to remove comprises removing one or more dielectric layers which were deposited in the first depositing.” This is indefinite, because claim 1 requires removal of a portion of the deposited layers, so the deposited layers element cannot be created after the etching.
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Cheng et al. (U.S. 2007/0246751).
As for claim 1,
Cheng teaches in figures 6-9 a method for manufacturing an integrated circuit, comprising:
manufacturing a first transistor configured for operation in a first range of voltages (configuring a transistor Vth is inherent because it is required for operation of the device’s voltage), comprising:
forming a first gate region (54) on a front face of a semiconductor substrate (50), said first gate region having sides perpendicular to the front face;
depositing dielectric layers (56/58) accumulating on the sides of the first gate region so as to form regions of spacers having a width in a direction perpendicular to the sides of the first gate region;
etching ( fig 7) to remove a part of the deposited dielectric layers which accumulated on the sides of the first gate region so as to reduce a width of the regions of spacers;
a first implanting of dopants (64) aligned on the regions of spacers to form first lightly doped conduction regions of the first transistor (lightly doped region [0019]); and
a second implanting (74) of dopants forming first conduction regions of the first transistor (high doped region,
said first conduction regions are more strongly doped than the lightly doped conduction regions. (high doping is higher concentration than light doping).
As for claim 2,
Cheng teaches the method according to claim 1:
wherein depositing dielectric layers comprises first depositing one or more dielectric layers before etching to remove (layers 56/58)
and depositing one or more dielectric layers (62/68/62) after etching to remove wherein etching to remove comprises removing one or more dielectric layers which were deposited in the first depositing.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Cheek et al. (U.S. 6,124,610).
As for claim 3,
Cheng teaches method according to claim 2, and teaches the first depositing comprises depositing a superposition of conformal layers of silicon oxide, silicon nitride [0019] but does not teach a third layer of silicon oxide.
However, Cheek teaches that the LDD spacer may comprise ONO [co2 ln51+}
It would have been obvious to one skilled in the art at the effective filing date of this application to use a third layer so that several layer can be selectively removed for multiple processes without exposing the gate electrode. [co3 ln3] One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 4,
Cheng teaches the method according to claim 1, but does not teach manufacturing a second transistor configured for operation in a second range of voltages comprising:
forming a second gate region on the front face of the semiconductor substrate, said second gate region having sides perpendicular to the front face; wherein the depositing dielectric layers further forms regions of spacers on the sides of the second gate region; and
masking to prevent removal, as a result of said etching to remove, of a part of the accumulations of dielectric layers deposited on the sides of the second gate region.
However, Cheek teaches in figures 1-4, manufacturing a second transistor configured for operation in a second range of voltages (a Vth is inherent as discussed above, and the transistors may be the same or different Vths) comprising:
forming a second gate region (left side) on the front face of the semiconductor substrate, said second gate region having sides perpendicular to the front face; wherein the depositing dielectric layers further forms regions of spacers on the sides of the second gate region; and
masking (26, figure 1) to prevent removal, as a result of said etching to remove, of a part of the accumulations of dielectric layers deposited on the sides of the second gate region.
It would have been obvious to one skilled in the art at the effective filing date of this application toad the method steps of Cheek to Cheng so that dissimilar transistors, here a p-mos and n-mos can be formed simultaneously. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Wu et a al. (U.S. 2011/0062507).
As for claim 5,
Cheng teaches the method according to claim 1, but does not teach manufacturing a third floating-gate transistor:
wherein forming the first gate region also forms a floating gate of the third floating-gate transistor; the method further comprising:
forming a tunnel dielectric layer on the front face; and
forming an electrically conductive layer on the tunnel dielectric layer.
However, Wu teaches in figure 1A, forming a third floating-gate transistor:
wherein forming the first gate region also forms a floating gate of the third floating-gate transistor (region 10 is a memory region [0036]); the method further comprising:
forming a tunnel dielectric layer (102) on the front face; and
forming an electrically conductive layer (104) on the tunnel dielectric layer.
It would have been obvious to one skilled in the art at the effective filing date of this application add the method of forming a 3rd transistor of Wu to the method of Cheng to increase the integration of the device and reduce manufacturing cost. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng
As for claims 6,
Cheng teaches the method according to claim 1, but does not teach manufacturing a fourth transistor configured for operation in a fourth range of voltages wherein said first implanting of dopants further forms fourth lightly doped conduction regions of the fourth transistor.
However, adding an additional transistor with a same LDD doping profile as the first transistor is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. Therefore, it would have been obvious to one skilled in the art at the invention was made to add additional transistors because
As for claim 7,
Cheng teaches the method according to claim 1, and teaches wherein etching to remove further removes a part of the dielectric layers accumulated on the front face of the semiconductor substrate. (top face of the conductor is cleared of 56 and 58 in figure 7)
Cheng does not teach manufacturing a fourth transistor configured for operation in a fourth range of voltages wherein said first implanting of dopants further forms fourth lightly doped conduction regions of the fourth transistor.
However, adding an additional transistor with a same LDD doping profile as the first transistor is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. Therefore, it would have been obvious to one skilled in the art at the invention was made to add additional transistors to the method of Cheng.
Conclusion
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893