DETAILED ACTION
This application, 18/230952, attorney docket 22RO0134US01/50649-01924, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to STMicroelectronics (Rousset) SAS, and claims foreign priority to FR2208512, filed 08/25/2022.
Response to Arguments
Applicant has amended claim 1 to include the two-step formation for the sidewall spacers and the implants, and correctly argues that the art of record, Cheng does not teach the method, so that rejection is withdrawn and a new rejection is presented below. Applicant’s amendment of claim 1 and cancellation of claim 2 address the previous §112b rejections, which are withdrawn, but new §112 rejections are presented below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the LDD aligned with the sidewall of the GP transistor must be shown or the feature cancelled from claim 1. Figures 10 and 11 show a different LDD than figure 14, and neither figure shows the implant aligned with the spacer. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 3-7 rejected under 35 U.S.C. 112(b) oas being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “depositing dielectric layers accumulating on the sides of the first and second gate regions so as to form regions of spacers
etching to remove the deposited dielectric layers which accumulated on the sides of the first gate region …so as to reduce a width of the regions of spacers for the first gate region;.” This is indefinite, because claim 1 requires removal of all of the deposited layers on the first gate, so the deposited layers element cannot have a measurable width, since it is gone
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Maekawa (U.S. 7,754,572).
As for claim 1,
Maekawa teaches in figures 2D, 4a to 4d, a method for manufacturing an integrated circuit, comprising:
manufacturing a first transistor 30A, configured for operation in a first range of voltages ([co5 ln 49+]), comprising:
forming a first gate region (33) and a second gate region (23) on a front face of a semiconductor substrate (11), said first and second gate regions having sides perpendicular to the front face;
depositing dielectric layers (25A, 26) accumulating on the sides of the first and second gate regions so as to form regions of spacers (fig.4a)
etching (4b) to remove the deposited dielectric layers which accumulated on the sides of the first gate region while leaving the deposited dielectric layers on the sides of the second gate region, so as to reduce a width of the regions of spacers for the first gate region;
depositing further dielectric layers (35) accumulating on the sides of the first gate region to form regions of further spacers for the first gate region;
a first implanting of dopants aligned on the regions of further spacers to form first lightly doped conduction regions (6e12 [co7 ln19]) of the first transistor (31, aligned with the side of the spaces adjacent the gate); and
a second implanting of dopants (34, 4D) aligned on the regions of further spacers (aligned with the expose face of the spacer) to form first conduction regions of the first transistor , where said first conduction regions are more strongly doped (co9 ln6]) than the lightly doped conduction regions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Maekawa in view of Cheek et al. (U.S. 6,124,610).
As for claim 3,
Maekawa teaches method according to claim 1, and teaches deposited dielectric layers comprise a superposition of conformal layers of silicon oxide [co12 ln3] and silicon nitride [co10 ln7] but does not teach a third layer of silicon oxide.
However, Cheek teaches that the LDD spacer may comprise ONO [co2 ln51+}
It would have been obvious to one skilled in the art at the effective filing date of this application to use a third layer so that several layer can be selectively removed for multiple processes without exposing the gate electrode. [co3 ln3] One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 4,
Maekawa teaches the method according to claim 1, and teaches that manufacturing a second transistor configured for operation in a second range of voltages comprising;
masking to prevent removal, as a result of said etching to remove, of a part of the accumulations of dielectric layers deposited on the sides of the second gate region (co12 ln 45])
and a third implanting of dopants aligned on the regions of spacers to form further lightly doped conduction regions (21, aligned with the inside of the spacer) of the second transistor;
wherein the second implanting of dopants forms second conduction regions (24) of the second transistor, where said second conduction regions are more strongly doped than the further lightly doped conduction regions. (dopant levels discussed above)
But Maekawa does not teach that the deposited further dielectric layers accumulate on the sides of the regions of spacers
However, Cheek teaches in figures 1-4, manufacturing a second transistor configured for operation in a second range of voltages includes deposited further dielectric layers (78A, figure 11) accumulate on the sides of the regions of spacers (deposited on both transistors)
It would have been obvious to one skilled in the art at the effective filing date of this application toad the method steps of Cheek to Maekawa so that dissimilar transistor HDD implant offsets, can be formed simultaneously. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Maekawa in view of Wu et a al. (U.S. 2011/0062507).
As for claim 5,
Maekawa teaches the method according to claim 1, but does not teach manufacturing a third floating-gate transistor:
wherein forming the first gate region also forms a floating gate of the third floating-gate transistor; the method further comprising:
forming a tunnel dielectric layer on the front face; and
forming an electrically conductive layer on the tunnel dielectric layer.
However, Wu teaches in figure 1A, forming a third floating-gate transistor:
wherein forming the first gate region also forms a floating gate of the third floating-gate transistor (region 10 is a memory region [0036]); the method further comprising:
forming a tunnel dielectric layer (102) on the front face; and
forming an electrically conductive layer (104) on the tunnel dielectric layer.
It would have been obvious to one skilled in the art at the effective filing date of this application add the method of forming a 3rd transistor of Wu to the method of Maekawa to increase the integration of the device and reduce manufacturing cost. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Maekawa
As for claims 6,
Maekawa teaches the method according to claim 1, but does not teach manufacturing a fourth transistor configured for operation in a fourth range of voltages wherein said first implanting of dopants further forms fourth lightly doped conduction regions of the fourth transistor.
However, adding an additional transistor with a same LDD doping profile as the first transistor is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. Therefore, it would have been obvious to one skilled in the art at the invention was made to add additional transistors because
As for claim 7,
Maekawa teaches the method according to claim 1, and teaches wherein etching to remove further removes a part of the dielectric layers accumulated on the front face of the semiconductor substrate. (top face of the conductor is cleared in figure 4c)
Maekawa does not teach manufacturing a fourth transistor configured for operation in a fourth range of voltages wherein said first implanting of dopants further forms fourth lightly doped conduction regions of the fourth transistor.
However, adding an additional transistor with a same LDD doping profile as the first transistor is a duplication of parts. It has been held that mere duplication or arrangement of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bermis Co., 193 USPQ8. Therefore, it would have been obvious to one skilled in the art at the invention was made to add additional transistors to the method of Maekawa.
Allowable Subject Matter
Claim 11 is allowed.
As for claim 11,
The prior art does not teach or make obvious forming multi-spacer sidewalls by the method recited, and then implanting both LDD and HDD using the spacers as alignment in the sequence recited in the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOHN A BODNAR/ Primary Examiner, Art Unit 2893
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