Prosecution Insights
Last updated: October 01, 2026
Application No. 18/231,247

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Aug 08, 2023
Priority
Oct 31, 2022 — RE 10-2022-0142581
Examiner
TRAN, TAN N
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
3 (Non-Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
974 granted / 1121 resolved
+18.9% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
33 currently pending
Career history
1158
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
50.5%
+10.5% vs TC avg
§102
33.8%
-6.2% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1121 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 2. Claim(s) 1 – 8, 12, 16 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (20180107037). With regard to claim 1, LEE discloses a display device (for example, see figs. 4, 7) comprising: a substrate (110); pixels (PX, for example see paragraph [0049]) disposed on the substrate (110); a plurality of signal lines (DL) inherently for applying a signal to the pixels (PX), the plurality of signal lines (DL) disposed on the substrate (110), the signal lines (DL) being spaced apart from one another and extending parallel to a first direction (for example, Y-direction functioning as a first direction), wide portions (portions 115A1, 115A2 as annotated in fig. 7 below), having a larger width, functioning as wide portions); and an identification pattern (referred to as “A” by examiner’s annotation shown in fig. 7 below; wherein the identification pattern “A” including the wide portions 115A1, 115A2 as annotated in fig. 7 below, having the numbers, symbols, letters, and pattern may indicate one or more corresponding data line identification numbers; for example, see paragraph [0069]) for identifying line numbers of the plurality of signal lines (DL), wherein the identification pattern (A) includes wide portions (115A1, 115A2) on one or more of the signal lines (DL) wherein the identification pattern (A) is expressed by a group of the wide portions (115A1, 115A2) and at least one wide portion (portions 115A1, 115A2 functions as at least one wide portion) in the group of the wide portions (an array of wide portions 115A1, 115A2) has a different length (referred to as “L1” and “L2” by examiner’s annotation shown in fig. 7 below; wherein the lengths L1, L2 are different) in the first direction (for example, Y-direction functioning as the first direction) as a part of the identification pattern (A). PNG media_image1.png 637 842 media_image1.png Greyscale PNG media_image2.png 501 601 media_image2.png Greyscale With regard to claim 2, LEE discloses the identification pattern (numbers, symbols, letters, and pattern, represented by the holes 115h may indicate one or more corresponding data line identification numbers; for example, see paragraph [0069]), forming wide portions, functioning as the identification pattern or functioning as a relief pattern in order to enhance the repair process (Although the applicant uses terms different to those of LEE to describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) With regard to claim 3, LEE discloses the identification pattern (numbers, symbols, letters, and pattern, represented by the holes 115h may indicate one or more corresponding data line identification numbers, functioning as an identification pattern) is one of a symbol, a letter, and a pattern (for example, see paragraph [0069]). With regard to claim 4, LEE discloses an orientation (a length orientation) of the identification pattern (the identification pattern forming in the portions 115A1, 115A2) is parallel to the first direction (Y-direction). With regard to claim 5, LEE discloses an orientation (a width orientation) of the identification pattern (the identification pattern forming in the portions 115A1, 115A2) crosses the first direction (Y-direction). With regard to claim 6, LEE discloses the identification pattern is expressed by a group of the wide portions (115A1, 115A2) formed on each of at least two lines (two lines DL of the data lines DL functioning as at least two lines) adjacent to each other in the second direction (X-direction) among the plurality of signal lines (the plurality of lines DL). With regard to claim 7, LEE discloses the lines (among lines DL of the data lines) are spaced apart from one another by a first width (referred to as “X1” by examiner’s annotation shown in fig. 7 below), and a width (referred to as “X2” by examiner’s annotation shown in fig. 7 below) of each of the plurality of wide portions (portions 115A1, 115A2) in the second direction (X-direction) is smaller than the first width (X1). PNG media_image3.png 732 468 media_image3.png Greyscale With regard to claim 8, LEE discloses the wide portions (115A1, 115A2) formed on each of at least two lines (DL) adjacent to each other in the second direction (X-direction) are spaced apart from each other. With regard to claim 12, LEE discloses a display device (for example, see figs. 4, 7) comprising: a substrate (110); pixels (PX, for example see paragraph [0049]) disposed on the substrate (110); a plurality of signal lines (DL) inherently for applying a signal to the pixels (PX), the plurality of signal lines (DL) comprising a first line (referred to as “DL1” by examiner’s annotation shown in fig. 7 below) and a second line (referred to as “DL2” by examiner’s annotation shown in fig. 7 below) disposed on the substrate (110), extending parallel to a first direction (for example, Y-direction functioning as a first direction) and spaced apart from each other, wherein the first line (DL1) includes first wide portions (referred to as “115A1”; “115A2” by examiner’s annotation shown in fig. 7 below) protruding in a second direction (for example, X-direction functioning as a second direction) and spaced apart from another in the first direction (Y-direction), wherein the second line (DL2) includes second wide portions (referred to as other portions “115A1”; “115A2” by examiner’s annotation shown in fig. 7 below) protruding in the second direction (X-direction) and spaced apart from another in the first direction (Y-direction), and wherein the first wide portions (115A1; 115A2) of the first line (DL1) and the second wide portions (other portions 115A1, 115A2) of the second line (DL2) adjacent to each other form an identification pattern (referred to as “A” by examiner’s annotation shown in fig. 7 below; wherein the identification pattern “A” including the wide portions 115A1, 115A2 functions as the identification pattern “A”, having the numbers, symbols, letters, and pattern may indicate one or more corresponding data line identification numbers; for example, see paragraph [0069]) for identifying line numbers of a plurality of lines (ones of among data lines DL functioning as a plurality of lines) wherein the identification pattern (A) is expressed by at least a group of the first wide portions (portions 115A1, 115A2) and the second wide portions (other portions 115A1, 115A2); at least one wide portion (115A1) in the group of the first wide portions (portions 115A1, 115A2) and second wide portions (other portions 115A2) has a different (referred to as “L1” and “L2” by examiner’s annotation shown in fig. 7 below; wherein the lengths L1, L2 are different) in the first direction (for example, Y-direction functioning as the first direction) as a part of the identification pattern (A). PNG media_image4.png 704 830 media_image4.png Greyscale PNG media_image2.png 501 601 media_image2.png Greyscale With regard to claim 16, LEE discloses the identification pattern (numbers, symbols, letters, and pattern, represented by the holes 115h may indicate one or more corresponding data line identification numbers; for example, see paragraph [0069]), forming wide portions 115, functioning as the identification pattern or functioning as a relief pattern in order to enhance the repair process (Although the applicant uses terms different to those of LEE to describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.) With regard to claim 17, LEE discloses the identification pattern (numbers, symbols, letters, and pattern, represented by the holes 115h may indicate one or more corresponding data line identification numbers, functioning as an identification pattern) is one of a symbol, a letter, and a pattern (for example, see paragraph [0069]). With regard to claim 18, LEE discloses an orientation (a length orientation) of the identification pattern (the identification pattern forming in the portions 115A1, 115A2)) is parallel to the first direction (Y-direction). With regard to claim 19, LEE discloses the first line (DL1) and the second line (DL2) are spaced apart from each other by a first width (referred to as “X1” by examiner’s annotation shown in fig. 7 below) in the second direction (X-direction), and wherein a width (referred to as “X2” by examiner’s annotation shown in fig. 7 below) of the second wide portion (another portion 115A1) in the second direction (X-direction) is greater than that of the first width (X1). PNG media_image5.png 684 488 media_image5.png Greyscale With regard to claim 20, LEE discloses the first line (DL1) extends through a center of the first wide portion (115A1 because the first line DL1 including the first wide portion 115A1 forming in the first line DL1), and the second line (DL2) extends through a center of the second wide portion (115A2 because the second line DL2 including the second wide portion 115A2 forming in the second line DL2). Claim Rejections - 35 USC § 103 3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (2018/0107037) in view of LIU et al. (2024/0258327). With regard to claim 9, LEE does not clearly disclose the first width ranges from 2 μm to 3 μm. However, LIU et al. discloses the spacing, between the data lines, functioning as first width is about 3 μm. (for example, see paragraph [0145]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LEE’s device to have the first width is 3 μm as taught by LIU et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. 5. Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (2018/0107037) in view of LIU et al. (12310111). With regard to claims 10, 11, LEE discloses the plurality of wide portions (115A1, 115A2) has a polygonal shape, but LEE does not clearly disclose all interior angles of the plurality of wide portions are obtuse degrees; and corners of each of the plurality of wide portions are rounded. However, LIU et al. (12310111) disclose all interior angles (referred to as “101A” by examiner’s annotation shown in fig. 3 below) of the plurality of wide portions (referred to as “101B” by examiner’s annotation shown in fig. 3 below) are obtuse degrees; and corners of each of the plurality of wide portions (101B) are rounded. PNG media_image6.png 534 756 media_image6.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LEE’s device to have all interior angles of the plurality of wide portions are obtuse degrees; and corners of each of the plurality of wide portions are rounded as taught by LIU et al. (12310111) in order to enhance high control overcurrent efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. 6. Claim(s) 13 - 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (2018/0107037) in view of Yee et al. (8330924). With regard to claim 13 - 15, LEE does not clearly disclose the second line at least partially overlaps the first line, and an insulating layer is interposed between the first line and the second line; wherein the first line and the first wide portion are formed integrally, and the second line and the second wide portion are formed integrally; and at least a portion of the first wide portion and at least a portion of the second wide portion overlap each other in a thickness direction. However, Yee et al. discloses disclose the second line (124b) at least partially overlaps the first line (124a), and an insulating layer (126) is interposed between the first line (124a) and the second line (124b); wherein the first line (124a) and the first wide portion (referred to as “124A1” by examiner’s annotation shown in fig. 7 below) are formed integrally, and the second line (124b) and the second wide portion (referred to as “124A2” by examiner’s annotation shown in fig. 7 below) are formed integrally; and at least a portion of the first wide portion (124A1) and at least a portion of the second wide portion (124A2) overlap each other inherently in a thickness direction. (for example, see figs. 6, 7C). PNG media_image7.png 635 574 media_image7.png Greyscale PNG media_image8.png 414 611 media_image8.png Greyscale Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LEE’s device to have disclose the second line at least partially overlaps the first line, and an insulating layer is interposed between the first line and the second line; wherein the first line and the first wide portion are formed integrally, and the second line and the second wide portion are formed integrally; and at least a portion of the first wide portion and at least a portion of the second wide portion overlap each other in a thickness direction as taught by Yee et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art. Response to Amendment 7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Conclusion 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN N TRAN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Show 1 earlier event
Nov 12, 2025
Non-Final Rejection (signed) — §102, §103
Dec 30, 2025
Non-Final Rejection mailed — §102, §103
Mar 25, 2026
Response Filed
Apr 24, 2026
Final Rejection mailed — §102, §103
Jun 23, 2026
Response after Non-Final Action
Jul 22, 2026
Request for Continued Examination
Jul 28, 2026
Response after Non-Final Action
Aug 21, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.9%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1121 resolved cases by this examiner. Grant probability derived from career allowance rate.

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