DETAILED ACTION
This Office action responds to Applicant’s amendments filed on 03/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-5, 7-10, and 14-21.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite.
The claim is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint regard as the invention.
Claim 7 (and any dependents) recites the limitation " wherein the second sub-gate structure is spaced apart from the drain region by a portion of the drift region, and an upper surface of the portion of the drift region is free of any conductive structure”. First, the claim previously does not define “a first sub-gate structure”. It is not clear if “the second sub-gate structure” is the same with “the second sub-gate insulating layer” that is described in claim 7. Also, there is insufficient antecedent basis for the limitation of “the second sub-gate structure”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 14-16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0077313) in view of Kim (US 10727300).
Regarding claim 1, Lin shows (see, e.g., Lin: fig. 1E) most aspects of the instant invention including a semiconductor structure 200, comprising:
A substrate 101
A drift region 103 located in the substrate
A source region 109 located in the substrate 101
A drain region 110 located in the substrate 101
A gate structure 106/107 disposed on the substrate 101 and located between the source region 109 and the drain region 110
The gate structure 106/107 comprising:
A first sub-gate structure 106 adjacent to the source region 109, the first sub-gate structure 106 comprising a first sub-gate insulating layer 104
A second sub-gate structure 107 adjacent to the drain region 110, the second sub-gate structure 107 comprising a second sub-gate insulating layer 104
The second sub-gate insulating layer 104 and the first sub-gate insulating layer 104 separated from each other
wherein:
The first sub-gate insulating layer 104 has a first thickness, the second sub-gate insulating layer 104 has a second thickness
However, Lin fails (see, e.g., Lin: fig. 1E) to show that the second thickness of the second sub-gate insulating layer 104 is greater than the first thickness of the first sub-gate insulating layer 104.
Kim, in a similar device to Lin, shows (see, e.g., Kim: figs. 1 and 2) that the second thickness of the second sub-gate insulating layer 320 is greater than the first thickness of the first sub-gate insulating layer 310 (see, e.g., Kim: col.5/II.59-67 – col.6/II.1-6). Kim also shows (see, e.g., Kim: figs. 1 and 2) that when the thin gate insulating film 310 having a relatively small thickness is used, the drain current may be increased; however, a thick gate insulating film 320 is used due to a high voltage being applied to the drain region 90 (see, e.g., Kim: col.6/II.17-25). The use of a thick gate insulating film 320 prevents the thin gate insulating film 310 from being broken due to high voltage (see, e.g., Kim: col.6/II.17-25). When a thin gate insulating film 310 is formed close to the drain region 90, the thin gate insulating film breaks and adversely affects the device's characteristics (see, e.g., Kim: col.6/II.17-25).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second thickness of the second sub-gate insulating layer of Kim that is greater than the first thickness of the first sub-gate insulating layer in the device of Lin, in order to prevent the thin gate insulating film from being broken due to high voltage, adversely affecting the device's characteristics.
Lin in view of Kim shows (see, e.g., Kim: figs. 1 and 2) that the second sub-gate structure 320/350 is spaced apart from the drain region 90 by a portion of the drift region 50, and an upper surface of the portion of the drift region 50 is free of any conductive structure.
Regarding claim 2, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) a connection region 111 located in the substrate 101 and connected to the first sub-gate insulating layer 104 and the second sub-gate insulating layer 104 (see, e.g., Lin: par. [0026]).
Regarding claim 3, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) a well region 101 located in the substrate 101, the source region 109, the drain region 110 and the connection region 111 located in the well region 101, wherein the well region 101 has a first conductivity type (see, e.g., Lin: par. [0021], where the well region 101 is p-type) , and the source region 109, the drain region 110 and the connection 111 each has a second conductivity type (see, e.g., Lin: par. [0021], where the source region 109, the drain region 110 and the connection 111 are of n-type) different from the first conductivity type.
Regarding claim 4, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) a drift region 103 is located in the well region 101, the drain region 110 located in the drift region 103, the second-sub gate structure 107 located on an intersection of the well region 101 and the drift region 103, wherein the drift region 103 has the second conductivity type (see, e.g., Lin: par. [0022], where the drift region 103 is n-type).
Regarding claim 5, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) the substrate 101 has an upper surface extending horizontally, and a lower surface of the first sub-gate insulating layer 104 and a lower surface of the second sub-gate insulating layer 104 are located at the upper surface of the substrate 101.
Regarding claim 7, Lin shows (see, e.g., Lin: fig. 1E) most aspects of the instant invention including a semiconductor structure 200, comprising:
A first transistor 200 formed in the first element area 200 of the substrate 101 and comprising a first gate structure 106/107
A drift region 103 located in the substrate 101
A drain region 110 located in the drift region 103
The first gate structure comprising a first sub-gate insulating layer 104 and a second sub-gate insulating layer 104 separated from each other
The second sub-gate insulating layer 104 being adjacent to the drain region 110
The first sub-gate insulating layer 104 having a first thickness, the second sub-gate insulating layer 104 having a second thickness
However, Lin fails (see, e.g., Lin: fig. 1E) to show that the second thickness of the second sub-gate insulating layer 104 is greater than the first thickness of the first sub-gate insulating layer 104.
Kim, in a similar device to Lin, shows (see, e.g., Kim: figs. 1 and 2) that the second thickness of the second sub-gate insulating layer 320 is greater than the first thickness of the first sub-gate insulating layer 310 (see, e.g., Kim: col.5/II.59-67 – col.6/II.1-6). Kim also shows (see, e.g., Kim: figs. 1 and 2) that when the thin gate insulating film 310 having a relatively small thickness is used, the drain current may be increased; however, a thick gate insulating film 320 is used due to a high voltage being applied to the drain region 90 (see, e.g., Kim: col.6/II.17-25). The use of a thick gate insulating film 320 prevents the thin gate insulating film 310 from being broken due to high voltage (see, e.g., Kim: col.6/II.17-25). When a thin gate insulating film 310 is formed close to the drain region 90, the thin gate insulating film breaks and adversely affects the device's characteristics (see, e.g., Kim: col.6/II.17-25).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second thickness of the second sub-gate insulating layer of Kim that is greater than the first thickness of the first sub-gate insulating layer in the device of Lin, in order to prevent the thin gate insulating film from being broken due to high voltage, adversely affecting the device's characteristics.
Lin in view of Kim also shows (see, e.g., Kim: fig. 9):
A substrate 10 having a first element area 100 and a second element area 400
A second transistor 400 formed in the second element area 400 of the substrate 10 and comprising a second gate structure 310c/350c
The second gate structure 310c/350c comprising a second gate insulating layer 310c, the second gate insulating layer 310c having a third thickness, the third thickness substantially equal to the first thickness (of gate insulating layer 310) (see, e.g., Kim: col.13/II.17-22).
Lin in view of Kim shows (see, e.g., Kim: figs. 1 and 2) that the second sub-gate structure 320/350 is spaced apart from the drain region 90 by a portion of the drift region 50, and an upper surface of the portion of the drift region 50 is free of any conductive structure.
Regarding claim 8, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the first sub-gate insulating layer 310 and the second gate insulating layer 310c are the same patterned film layer (see, e.g., Kim: col.13/II.17-22).
Regarding claim 9, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the first transistor 100 is a high-voltage transistor (see, e.g., Kim: col.12/II.46-56), and the second transistor 400 is a low-voltage transistor (see, e.g., Kim: col.13/II.17-22).
Regarding claim 14, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that:
The substrate 10 has a third element area 200
The semiconductor structure further comprises a third transistor 200 formed in the third element area 200 of the substrate 100 and comprising a third gate structure 350a/320a
The third gate structure 350a/320a comprises a third gate insulating layer 320a, and the third gate insulating layer 320a has a fourth thickness 320a substantially equal to the second thickness 320
Regarding claim 15, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the second sub-gate insulating layer 320 and the third insulating layer 320a are the same pattern film layer (see, e.g., Kim: col.12/II.57-67 – col.13/II.1-3).
Regarding claim 16, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the second transistor 400 is a low-voltage transistor see, e.g., Kim: col.13/II.17-22), and the third transistor 200 is an I/O transistor (see, e.g., Kim: col.11/II.65-67 – col.12/II.1-5).
Regarding claim 18, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) that:
The first transistor 200 comprises a source region 109, a drain region 110, and a connection region 111 located in the substrate 101
The first sub-gate insulating layer 104 is adjacent to the source region 109, the second sub-gate insulating layer 104 is adjacent to the drain region 110, and the connection region 111 is connected to the first sub-gate insulating layer 104 and the second sub-gate insulating layer 104
Regarding claim 19, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) a well region 101 located in the substrate 101, the source region 109, the drain region 110 and the connection region 111 located in the well region 101, wherein the well region 101 has a first conductivity type (see, e.g., Lin: par. [0021], where the well region 101 is p-type) , and the source region 109, the drain region 110 and the connection 111 each has a second conductivity type (see, e.g., Lin: par. [0021], where the source region 109, the drain region 110 and the connection 111 are of n-type) different from the first conductivity type.
Regarding claim 20, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) that the drift region 103 is located in the well region 101, the second-sub gate structure 107 located on an intersection of the well region 101 and the drift region 103, wherein the drift region 103 has the second conductivity type (see, e.g., Lin: par. [0022], where the drift region 103 is n-type).
Regarding claim 21, Lin in view of Kim shows (see, e.g., Lin: fig. 1E) that the substrate 101 has an upper surface extending horizontally, and a lower surface of the first sub-gate insulating layer 104 and a lower surface of the second sub-gate insulating layer 104 are substantially coplanar with the upper surface of the substrate 101 when viewed horizontally from a cross-section perpendicular to the upper surface of the substrate 101.
Claims 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kim in further view of Liao (US 2023/0223300).
Regarding claim 10, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the second gate insulating layer 310c of the low-voltage transistor 400 has a third thickness.
However, Lin in view of Kim fails (see, e.g., Kim: fig. 9) to show that the third thickness of the second gate insulating layer 310c of the low-voltage transistor 400 is less than or equal to 25 angstroms (A). Liao, in a similar device of Lin in view of Kim, shows (see, e.g., Liao: fig. 10) that thickness of the gate insulating layer 411 of the transistor is less than 50 angstroms (A) (see, e.g., Liao: par. [0091]). Liao also shows (see, e.g., Liao: fig. 10) that the gate insulating layer 411 is part of the gate structure 410, which is essential for the transistor’s functioning (see, e.g., Liao: par. [0091] – [0094]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the gate insulating layer of Liao in the device of Lin in view of Kim, in order to make a gate structure that is essential for the transistor’s functioning.
However, the differences in the thicknesses of gate insulating layers of low-voltage transistors will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned thicknesses of gate insulating layers of low-voltage transistors, and Liao has identified such thicknesses of gate insulating layers of low-voltage transistors as result-effective variables subject to optimization (see, e.g., Liao: par. [0091] – [0094]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Lin in view of Kim.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 17, Lin in view of Kim shows (see, e.g., Kim: fig. 9) that the second gate insulating layer 310c of the low-voltage transistor 400 has a third thickness and the third gate insulating layer 320a of the I/O transistor 200 has a fourth thickness.
However, Lin in view of Kim fails (see, e.g., Kim: fig. 9) to show that the third thickness of the second gate insulating layer 310c of the low-voltage transistor 400 is less than or equal to 25 angstroms (A), and the fourth thickness of the third gate insulating layer 320a of the I/O transistor 200 is less than or equal to 40 angstroms (A).
Liao, in a similar device of Lin in view of Kim, shows (see, e.g., Liao: fig. 10) that thickness of the gate insulating layer 411 of the transistor is less than 50 angstroms (A) (see, e.g., Liao: par. [0091]). Liao also shows (see, e.g., Liao: fig. 10) that the gate insulating layer 411 is part of the gate structure 410, which is essential for the transistor’s functioning (see, e.g., Liao: par. [0091] – [0094]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the thickness of the gate insulating layer of Liao in the device of Lin in view of Kim, in order to make a gate structure that is essential for the transistor’s functioning.
However, the differences in the thicknesses of gate insulating layers of low-voltage transistors and I/O transistors will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph 33 of the mentioned thicknesses of gate insulating layers of low-voltage transistors and I/O transistors, and Liao has identified such thicknesses of gate insulating layers of low-voltage transistors and I/O transistors as result-effective variables subject to optimization (see, e.g., Liao: par. [0091] – [0094]), it would have been obvious to one of ordinary skill in the art to use these thickness values in the device of Lin in view of Kim.
Response to Arguments
Examiner has read and considered Applicants’ arguments, and finds them not persuasive in view of the new grounds of rejection. Applicants’ arguments for claims 1, and 7 have been considered but are moot in view of the new grounds of rejection.
The applicants argue:
Lin fails to anticipate or render obvious the amended limitation of "… the second sub-gate structure is spaced apart from the drain region by a portion of the drift region, and an upper surface of the portion of the drift region is free of any conductive structure", as recited in claims 1, and 7.
The examiner responds:
In view of the new grounds of rejection, Lin in view of Kim clearly shows (see, e.g., Kim: figs. 1 and 2) that the second sub-gate structure 320/350 is spaced apart from the drain region 90 by a portion of the drift region 50, and an upper surface of the portion of the drift region 50 is free of any conductive structure.
The structure 270 above the drift region 50 is not a conductive structure, it is dielectric protective film, which is a silicide blocking insulating film 270 formed between the drain region 90 and the thick gate insulating film 320 on the substrate 10.
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814