DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
3. This action is in response to Applicant’s Request for Reconsideration dated 03/12/2026.
4. Claims 1-19 and 21 are currently pending.
5. Claims 1, 4, 6-7, 12-14, 16, and 18-19 have been amended.
6. Claim 20 has been cancelled.
7. Claim 21 has been added.
Claim Rejections - 35 USC § 112
8. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
9. Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 21:
Claim 21 recites “wherein the processing chamber includes a single plasma processing space therein without an ion trap”. Nothing in the specification at the time of filing conveys to one of ordinary skill in the art that applicant had possession of the claimed invention. The mere absence of a positive limitation is NOT basis for an exclusion [MPEP 2173.05(i)]. To the extent that applicant may attempt to rely on the drawings, it is noted that the drawings are NOT all inclusive. In fact, the written specification specifically mentions that several structures are “not illustrated”.
Claim Rejections - 35 USC § 102
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
11. Claim(s) 1-10, 13-14, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maruyama et al (US 2018/0144948).
Regarding claim 1:
Maruyama teaches a substrate processing apparatus (plasma processing apparatus, 100) [fig 11 & 0089], comprising: a processing chamber (processing container, 120) [fig 11 & 0089]; a support (mounting stage, 14) in the processing chamber (120) and on which a processing target object (W) including a first region (EL) made of silicon oxide (silicon oxide film) is placed [fig 11 & 0023, 0090]; and a control circuit (control unit, 42) [fig 11 & 0035, 0089], wherein a) the control circuit (45) is configured to cause the substrate processing apparatus to supply a process gas (processing gas) containing fluorocarbon and a rare gas (fluorocarbon gas and a rare gas) to the processing chamber [fig 11 & 0035, 0039], b) the control circuit (42) is configured to cause the substrate processing apparatus (100) to plasma-process the processing target object by a first plasma of the process gas generated under a first plasma generation condition (step, ST2) [fig 4 & 0038-0040], c) the control circuit (42) is configured to cause the substrate processing apparatus (100) to plasma-process the processing target object in which a bias potential (high-frequency bias, LF) is generated on the processing target object by a second plasma of the process gas generated under a second plasma generation condition (step, ST3) different from the first plasma generation condition (step, ST2) [fig 4 & 0042-0043, 0045], the b) (step, ST2) and the c) (step, ST3) being performed in a same plasma processing space (S) of the processing chamber (both ST2 and ST3 perform a process on the wafer in space S) [fig 11 & 0041-0042, 0089], and d) the control circuit (42) is configured to cause the substrate processing apparatus (100) to repeat the b) and the c) (execution of the sequence SQ including the step ST2 and the step ST3 is performed again) [fig 4 & 0046].
Regarding claim 2:
Maruyama teaches the support (14) includes a chuck (22) to receive the processing target object (W) and a lower electrode (20) under the chuck (22) [fig 11 & 0090-0091].
Regarding claim 3:
Maruyama teaches an upper electrode (344) spaced apart from the chuck (22), the upper electrode (344) being on an opposite side of the chuck (22) than the lower electrode (20) [fig 11 & 0092].
Regarding claim 4:
Maruyama teaches the upper electrode (344) receives the process gas (processing gas) and includes gas outlets (400h) to supply the process gas to the processing chamber in a) [fig 4, 11 & 0094].
Regarding claim 5:
Maruyama teaches the first plasma generation condition in b) (step, ST2) includes supplying a first RF power having a first frequency (high-frequency wave HF) to the upper electrode (344) [fig 4, 11 & 0094].
Regarding claim 6:
Maruyama teaches the first plasma generation condition in b) (step, ST2) includes supplying no power to the lower electrode (high-frequency bias LF is not supplied to 20) [fig 4, 11 & 0094].
Regarding claim 7:
Maruyama teaches the second plasma generation condition in c) (step, ST3) includes supplying the bias potential (high-frequency bias LF) having a second frequency (400 kHz to 27.12 MHz), less than the first frequency (may be 40 MHz or 60 MHz), to the lower electrode (20) [fig 4, 11 & 0027, 0032, 0095].
Regarding claims 8-10:
Maruyama teaches the second plasma generation condition in c) (step, ST3) includes supplying no power to the upper electrode (see fig 4) [fig 4, 11 & 0095]; wherein the second plasma generation condition in c) (step, ST3) includes supplying the bias potential (LF) to the lower electrode (20) [fig 4, 11 & 0095]; and wherein the second plasma generation condition in c) (step, ST3) further includes supplying no power to the upper electrode (see fig 4) [fig 4, 11 & 0095].
Regarding claim 13:
Maruyama teaches a substrate processing apparatus (plasma processing apparatus, 100) [fig 11 & 0089], comprising: a processing chamber (processing container, 120) [fig 11 & 0089]; a support (mounting stage, 14) in the processing chamber (120) and on which a processing target object (W) including a first region (EL) made of silicon oxide (silicon oxide film) is placed [fig 11 & 0023, 0090]; and a control circuit (control unit, 42) [fig 11 & 0035, 0089], wherein the control circuit (45) is configured to a) supply a process gas (processing gas) containing fluorocarbon and a rare gas (fluorocarbon gas and a rare gas) to the processing chamber [fig 11 & 0035, 0039]; b) (step, ST2) supply a first RF power (HF) having a first frequency range (may be 40 MHz or 60 MHz) into the processing chamber from a first power supply (HFS) to generate a first plasma of the process gas from the first power supply (HFS) [fig 4, 11 & 0032, 0094]; and c) (step, ST3) supply a second RF power (LF) having a second frequency range (400 kHz to 27.12 MHz) lower than the first frequency range (may be 40 MHz or 60 MHz) into the processing chamber from a second power supply (LFS), separate from the first power supply (HFS), to generate a second plasma of the process gas, to draw ions contained in the second plasma to the processing target object (ions are drawn into the wafer W), wherein the first frequency range (may be 40 MHz or 60 MHz) and the second frequency range do not overlap (400 kHz to 27.12 MHz) [fig 4, 11 & 0027, 0032, 0095], in the b) (step, ST2) and the c) (step, ST3), supply and stop of the supply of the first RF power (HF) having the first frequency range and the second RF power (LF) having the second frequency range are controlled independently of each other for each predetermined frequency (see fig 4), the b) (step, ST2) and the c) (step, ST3) being performed in a same plasma processing space (S) of the processing chamber (both ST2 and ST3 perform a process on the wafer in space S), and apply only the first RF power (HF) at the first frequency range from the first power supply (HFS) during b) (step, ST2) and applying only the second RF power (LF) at the second frequency range from the second power supply (LFS) during c) (step, ST3) [fig 4, 11 & 0041-0042, 0089, 0094-0095].
Regarding claim 14:
Maruyama teaches the support (14) includes a chuck (22) to receive the processing target object (W) and a lower electrode (20) under the chuck (22) [fig 11 & 0090-0091] and further comprising an upper electrode (344) spaced apart from the chuck (22), the upper electrode (344) being on an opposite side of the chuck (22) than the lower electrode (20) [fig 11 & 0092], wherein the first RF power (HF) is supplied only to the upper electrode (344) and the second RF power (LF) is supplied only to the lower electrode (20) [fig 4, 11 & 0094-0095].
Regarding claim 21:
Maruyama teaches the processing chamber (120) includes a single plasma processing space (S) therein without an ion trap, both the b) (step, ST2) and c) (step, ST3) being processed in the single plasma processing space of the processing chamber (both ST2 and ST3 perform a process on the wafer in space S) [fig 11 & 0041-0042, 0089].
Claim Rejections - 35 USC § 103
12. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claim(s) 11-12 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama et al (US 2018/0144948) as applied to claims 1-10, 13-14, and 21 above, and further in view of Kanakasabapathy et al (US 6,875,700).
The limitations of claims 1-10, 13-14, and 21 have been set forth above.
Regarding claims 11-12:
Murayama does not specifically disclose e) the control circuit is configured to cause the substrate processing apparatus to stop the plasma-process under the first plasma generation condition and delay generation of the bias potential in c); and wherein the control circuit is configured to cause the substrate processing apparatus to repeat the b), the e), and the c), in that order.
Kanakasabapathy teaches stopping the plasma-process under the first plasma generation condition (terminated at time t1) and delay generation of the bias potential in c) (delay, 22) [fig 2 & col 5-6, lines 53-4]; and causing the substrate processing apparatus to repeat the b) (t0-t1), the e) (22 at t1-t2), and the c) (t2-t0’), in that order [fig 2 & col 5-6, lines 53-4].
It would have been obvious to one skilled in the art before the effective filing date to modify the control circuit of Murayama to further comprise a delay e) between b) and c), as in Kanakasabapathy, to allow for electron population to fall to an insignificant level which provides one or more of the following advantages: complete control over ion bombardment energy; reduced risk of charging up; maximal etch efficiency, especially in the fraction of available electron-free plasma time during which ion bombardment actually occurs; capability to combine positive-ion and negative-ion bombardment; and capability to combine maximal etch rate with minimal electron impingement [Kanakasabapathy – col 3, lines 30-56].
Regarding claims 15-16:
Murayama does not specifically disclose the control circuit is further configured to d) stop supply of the first RF power and delay the supply of the second RF power; and wherein the control circuit is configured to cause the substrate processing apparatus to repeat the b), the e), and the c), in that order.
Kanakasabapathy teaches d) stopping supply of the first RF power (terminated at time t1) and delay the supply of the second RF power (delay, 22) [fig 2 & col 5-6, lines 53-4]; and causing the substrate processing apparatus to repeat the b) (t0-t1), the d) (22 at t1-t2), and the c) (t2-t0’), in that order [fig 2 & col 5-6, lines 53-4].
It would have been obvious to one skilled in the art before the effective filing date to modify the control circuit of Murayama to further comprise a delay d) between b) and c), as in Kanakasabapathy, to allow for electron population to fall to an insignificant level which provides one or more of the following advantages: complete control over ion bombardment energy; reduced risk of charging up; maximal etch efficiency, especially in the fraction of available electron-free plasma time during which ion bombardment actually occurs; capability to combine positive-ion and negative-ion bombardment; and capability to combine maximal etch rate with minimal electron impingement [Kanakasabapathy – col 3, lines 30-56].
Regarding claim 17:
Although modified Murayama does not specifically disclose “the control circuit is configured to delay the supply of the second RF power by between 12% and 25% of one cycle”, modified Murayama teaches the delay is a result-effective variable [Kanakasabapathy – col 5, lines 21-42]. It would have been obvious to one skilled in the art before the effective filing date to discover the optimum value for the delay based on the given plasma condition through routine experimentation in order to reduce the electron population to an insignificant level [Kanakasabapathy – col 5, lines 21-42]. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art [MPEP 2144.05].
15. Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable Maruyama et al (US 2018/0144948) in view of Kanakasabapathy et al (US 6,875,700).
Regarding claim 18:
Maruyama teaches a substrate processing apparatus (plasma processing apparatus, 100) [fig 11 & 0089], comprising: a control circuit (control unit, 42) [fig 11 & 0035, 0089], wherein the control circuit (42) is configured to a) supply a process gas (processing gas) containing fluorocarbon and a rare gas (fluorocarbon gas and a rare gas) to a processing chamber (processing container, 120) in which a support (mounting stage, 14) for placing a processing target object (W) including a first region (EL) made of silicon oxide (silicon oxide film) is arranged [fig 11 & 0023, 0035, 0039, 0089-0090]; b) plasma-process the processing target object (W) by a first plasma of the process gas generated under a first plasma generation condition (step, ST2) [fig 4 & 0038-0040]; c) plasma-process the processing target object (W) in which a bias potential (high-frequency bias, LF) is generated on the processing target object (W) by a second plasma of the process gas generated under a second plasma generation condition (step, ST3) different from the first plasma generation condition (step, ST2) [fig 4 & 0042-0043, 0045], and e) repeat the b) and the c) , in that order (execution of the sequence SQ including the step ST2 and the step ST3 is performed again) [fig 4 & 0046].
Murayama does not specifically disclose the control circuit is further configured to d) stop the plasma-process under the first plasma generation condition in b) and delay plasma-process under the second plasma generation condition in c); and repeat the b), the d), and the c), in that order.
Kanakasabapathy teaches d) stopping the plasma-process under the first plasma generation condition (terminated at time t1) in b) (t0-t1) and delay plasma-process under the second plasma generation condition (delay, 22) in c) (t2-t0’) [fig 2 & col 5-6, lines 53-4]; and repeat the b) (t0-t1), the d) (22 at t1-t2), and the c) (t2-t0’), in that order [fig 2 & col 5-6, lines 53-4].
It would have been obvious to one skilled in the art before the effective filing date to modify the control circuit of Murayama to further comprise a delay d) between b) and c), as in Kanakasabapathy, to allow for electron population to fall to an insignificant level which provides one or more of the following advantages: complete control over ion bombardment energy; reduced risk of charging up; maximal etch efficiency, especially in the fraction of available electron-free plasma time during which ion bombardment actually occurs; capability to combine positive-ion and negative-ion bombardment; and capability to combine maximal etch rate with minimal electron impingement [Kanakasabapathy – col 3, lines 30-56].
Regarding claim 19:
Maruyama teaches the support (14) includes a chuck (22) to receive the processing target object (W) and a lower electrode (20) under the chuck (22) [fig 11 & 0090-0091] and the processing chamber includes an upper electrode (344) spaced apart from the chuck (22), the upper electrode (344) being on an opposite side of the chuck (22) than the lower electrode (20) [fig 11 & 0092], wherein the first plasma generation condition (step, ST) includes supplying power (HF) only to the upper electrode (344) and the second plasma generation condition (step, ST3) includes supplying power (LF) only to the lower electrode (20) [fig 4, 11 & 0094-0095].
Response to Arguments
16. Applicant’s arguments, see Remarks, filed 03/12/2026, with respect to the rejection of claim(s) 12-17 and 19-20 under 35 USC 112(b) have been fully considered and are persuasive. The rejection of claim(s) 12-17 and 19-20 has been withdrawn in view of the amendments to claim(s) 12-14, 16, and 19.
17. Applicant's arguments, see Remarks, filed 03/12/2026, with respect to the rejection of claim(s) 1-10, 13-14, and 18-19 under 35 USC 102(a)(1) and claim(s) 11-12, 15-17, and 20 under 35 USC 103 have been fully considered but they are not persuasive.
Regarding claims 1 and 13:
Applicant argues that steps ST2 and ST3 of Murayama are performed in different internal spaces S2 and S1.
In response, examiner disagrees. Both of steps ST2 and ST3 perform a process on the wafer in space S1 [0041-0042]. Furthermore, the embodiment relied upon discloses a single internal space S [fig 11 & 0089].
Regarding claim 18:
Applicant argues that the ion trap 40 of Murayama provides control over generated ions. The delay of Kanakasabapathy improves ion and charge control. As such, the purported rationale for modifying Murayama is specious. The effect is already exhibited by the unmodified structure of Murayama.
In response, it is noted 40 of Murayama provides for passive control over generated ions. The delay of Kanakasabapathy is an active control thereby enabling complete control over ion bombardment energy. Nevertheless, applicant’s argument does NOT address the many other rationales set forth in the rejection of record. Specifically, it would have been obvious to one skilled in the art before the effective filing date to modify the control circuit of Murayama to further comprise a delay d) between b) and c), as in Kanakasabapathy, to allow for electron population to fall to an insignificant level which provides one or more of the following advantages: complete control over ion bombardment energy; reduced risk of charging up; maximal etch efficiency, especially in the fraction of available electron-free plasma time during which ion bombardment actually occurs; capability to combine positive-ion and negative-ion bombardment; and capability to combine maximal etch rate with minimal electron impingement [Kanakasabapathy – col 3, lines 30-56].
Conclusion
18. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hudson et al (US 2018/0286707) teaches a first plasma condition (209) and a second plasma condition (213) [fig 2B].
19. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN R KENDALL whose telephone number is (571)272-5081. The examiner can normally be reached Mon - Thurs 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Benjamin Kendall/Primary Examiner, Art Unit 2896