DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on 12/2/2025 is acknowledged. Furthermore, the Examiner acknowledges the cancellation of non-elected claims 17-20, and the addition of newly added claims 21-24 directed to the elected invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the phrase “…forming a pattern the protective layer to expose the first fin structure” (emphasis added). This appears to be an incomplete sentence, as it is unclear if the claim is intended to mean forming a pattern from the protective layer, forming a pattern over/on the protective layer, or some other type of process.
¶ 0046 discusses forming pattern stack 228/230 over protective layer 226, and ¶ 0059 discusses forming a pattern from patterning (removing portions of) protective layer 226. However, the claims are not specific to either of these patterning processes. For the purposes of compact prosecution, the Examiner has interpreted claim 13 to mean “prior to recess etching the first fin structure, forming a pattern on the protective layer to expose the first fin structure.”
Claims 14-15 depend on claim 13, and are rejected under 35 USC § 112(b) for implicitly including the indefinite subject matter above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-16 and 21-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (PG Pub. No. US 2023/0006052 A1).
Regarding claim 1, Yu teaches a method for fabricating a semiconductor device, comprising:
forming a first device feature (¶ 0024: 130) on a semiconductor substrate (¶ 0024: 130 formed on substrate 100);
forming a second device feature (¶ 0022: fin structure including active pattern 102 and stacked layers 112, 122) on the semiconductor substrate (fig. 2: 102/112/122 formed on 100), wherein the first device feature is adjacent the second device feature (fig. 2: 130 adjacent to 102/112/122), and the second device feature is taller than the first device feature relative to the semiconductor substrate (fig. 2: 102/112/122 taller than 130);
depositing a protective layer (¶ 0030: 180) over the first device feature and the second device feature (¶ 0033 & fig. 8: at least portion 183 of layer 180 deposited over 102/112/122);
etching back the protective layer to reveal a portion of the second device feature while the first device feature remains covered by the protective layer (¶ 0035 & fig. 8: at least a top portion of 183 etched back to reveal 102/112/122 while 130 remains covered by 183); and
etching the second device feature to form an opening (¶ 0035 & fig. 8: exposed portion of 102/112/122 etched to form opening 210) below a top surface of the protective layer (fig. 8: 210 formed below remaining top surface of 183).
Regarding claim 4, Yu teaches the method of claim 1, further comprising:
forming a pattern (¶¶ 0025, 0030, 0033: patterned layers 170, 190 and/or 200) over the second device feature prior to etching the second device feature (figs. 7-8: 170, 190 and/or 200 formed over 102/112/122 prior to etching 102/112/122).
Regarding claim 5, Yu teaches the method of claim 4, wherein the second device feature is a fin structure extending from the semiconductor substrate (¶ 0022 & fig. 2: 102/112/122 comprises a fin structure vertically extending from 100), and the first device feature is an isolation layer (¶ 0024: 130 comprises an isolation pattern) formed on the semiconductor substrate and around a lower portion of the fin structure (fig. 2: 130 formed on 100 and around fin portion 102).
Regarding claim 6, Yu teaches the method of claim 5, further comprising depositing a spacer layer (¶ 0027: 140) over the first device feature and the second device feature prior to depositing the protective layer (fig. 4: 140 deposited over 130 and 102/112/122 prior to depositing 180).
Regarding claim 7, Yu teaches the method of claim 6, further comprising removing a portion of the spacer layer deposited on a top surface of the first device feature and a top surface of the second device feature (fig. 8: at least a portion of 140 removed from top surfaces of 130 and 102/112/122).
Regarding claim 8, Yu teaches the method of claim 7, wherein removing the portions of the spacer layer is performed after etching back of the protective layer (fig. 24: at least a portion of 140 removed after etching back portion 183).
Regarding claim 9, Yu teaches the method of claim 7, wherein removing the portions of the spacer layer is performed prior to depositing the protective layer (fig. 7: portion of 140 removed prior to depositing 180).
Regarding claim 10, Yu teaches the method of claim 4, wherein forming the pattern comprises:
depositing a pattern stack (¶¶ 0030, 0033: 190/200) over the protective layer prior to etching back the protective layer (¶ 0035, fig. 8: 190/200 formed over 180 prior to etching back 180/183 to form 210).
Regarding claim 11, Yu teaches the method of claim 4, wherein forming the pattern comprises:
depositing a pattern stack (¶¶ 0044, 0046: 230/240) over the protective layer after etching back the protective layer (figs. 13-16: 230/240 deposited over portion 183 after etching back 180).
Regarding claim 12, Yu teaches a method for fabricating a semiconductor device, comprising:
forming a first fin structure and a second fin structure over a semiconductor substrate (¶ 0022 & fig. 2: first and second fin structures, including portions of patterns 102/104 and layers 112, 114, 122 and 124, formed over substrate 100);
forming an isolation layer (¶ 0024: 130) around lower portions of the first and second fin structures (fig. 2: 130 formed around lower fin portions 102 and 104);
forming a sacrificial gate structure (¶ 0027: 150) over the first and second fin structures and the isolation layer (figs. 3-4: 150 formed over 102/112/122, 104/114/124 and 130);
depositing a spacer layer (¶ 0028: 160) over the isolation layer, the first and second fin structures, and the sacrificial gate structure (figs. 6-7: 160 at least indirectly deposited over 130, 102/112/122 and 104/114/124);
immersing the first and second fin structures and the sacrificial gate structure in a protective layer (¶ 0030: 102/112/122, 104/114/124 and 150 immersed In layer 180);
etching back the protective layer so that a top surface of the protective layer is below a top surface of the first fin structure (fig. 8: 180, including portions 182 and 183, etched back such that at least one top surface of 180 is below a top surface of 102/112/114 protected by gate 170, and/or top surface of 104/114/124 protected by layer 200); and
recess etching the first fin structure while the isolation layer is covered by the protective layer (¶¶ 0035, 0048 & figs. 8, 16: fin 102/112/122 recessed while 130 is covered by a portion of protective layer 180, and/or 104/114/124 recessed while 130 is covered by a second portion of protective layer 180).
Regarding claim 13, Yu teaches the method of claim 12, further comprising:
prior to recess etching the first fin structure, forming a pattern on the protective layer to expose the first fin structure (¶ 0033 & fig. 8: 200 formed on 180 to expose 102/112/122 prior to recessing 102/112/122; alternatively, ¶ 0046 & fig. 16: 240 formed on protective layer portion 183 to expose 104/114/124 prior to recessing 104/114/124).
Regarding claim 14, Yu teaches the method for claim 13, wherein forming the pattern is performed prior to etching back the protective layer (fig. 8: 200 formed before etching back first portion of 180, and/or fig. 16: 240 formed before etching back second portion of 180).
Regarding claim 15, Yu teaches the method of claim 13, wherein forming the pattern is performed after etching back the protective layer (fig. 16: 240 formed after etching back first portion of 180).
Regarding claim 16, Yu teaches the method of claim 12, further comprising depositing an enhancing layer over the spacer layer (¶ 0030 & fig. 6: 190 deposited over 160).
Regarding claim 21, Yu teaches a method, comprising:
forming a fin structure (¶ 0022 & fig. 2: fin structure including elements 102/112/124 or 104/114/124);
forming an isolation layer (¶ 0024: 130) around a lower portion of the fin structure (fig. 2: 130 formed around lower fin portion 102 or 104);
forming a gate structure (¶ 0027: 150) over the fin structure (fig. 4: 150 formed over 102/112/122 or 104/114/124);
forming a spacer layer (¶ 0030: 190), wherein the spacer layer comprises a sidewall spacer disposed on a sidewall of the gate structure (fig. 7: 190 includes portion 192 disposed on sidewall of 150) and on a bottom spacer disposed on a top surface of the isolation layer (fig. 8: 190 includes portion 193 disposed on spacer 183 disposed on top surface of 130);
etching back the fin structure (¶ 0035 & fig. 8: 102/112/114 etched back, or ¶ 0048 & fig. 16: 104/114/124 etched back);
forming a source/drain region (¶¶ 0040, 0053: 220 or 260) in connection to the fin structure (fig. 19: 220 formed in connection with fin portion 102, 260 formed in connection with fin portion 104);
forming a contact etch stop layer (CESL) (¶ 0057: 270) on the source/drain region (fig. 22: 270 formed on 220 and 260); and
forming an interlayer dielectric layer (IDL) (¶ 0059: 280) on the CESL (fig. 24: 280 formed on portions of 270), wherein the bottom spacer is disposed between the CESL and the isolation layer (fig. 27: portion 182 disposed between a leftmost portion of 270 and a middle or rightmost portion of 280).
Regarding claim 22, Yu teaches the method of claim 21, further comprising forming a protective layer (¶¶ 0033, 044, 046: 200, 230 or 240) disposed on the bottom spacer prior to etching back the fin structure (fig. 8: 200 disposed on a portion of 180 prior to etching back 102/112/124; alternatively, 230 and 240 disposed on portion 183 prior to etching back 104/114/124).
Regarding claim 23, Yu teaches the method of claim 22, wherein the spacer layer further comprises a fin sidewall spacer (¶ 0033: 183) in contact with the source/drain region and the protective layer (fig. 11: 183 in contact with 220 and portion of 190).
Regarding claim 24, Yu teaches the method of claim 22, wherein a top surface of the protective layer is above the fin sidewall spacer (fig. 11: top surface of 190 above 183), and the protective layer is in contact with the source/drain region (fig. 10: portion of 190 in contact with 220).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Vellianitis (PG Pub. No. US 2021/0125986 A1).
Regarding claim 2, Yu teaches the method of claim 1, including etching back a protective layer (fig. 8: at least a portion of 180 etched back).
Yu does not teach the method further comprising planarizing the protective layer prior to etching back the protective layer.
Vellianitis teaches a method comprising planarizing a protective layer (¶ 0056: fin spacer 450A/450B planarized) prior to etching back the protective layer (¶ 0057: at least a portion of 450A/450B subsequently etched back).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Yu with the protective layer planarization of Vellianitis, as a means to provide a uniform surface across a plurality of fins, ensuring minimal process variation across the substrate.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the planarization of Vellianitis could be combined with the method of Yu with no change in their respective functions, yielding nothing more than predictable results.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Yu et al. (PG Pub. No. US 2022/0262925 A1, hereinafter referenced as ‘Yu-925’).
Regarding claim 3, Yu teaches the method of claim 1, comprising etching back the protective layer (figs. 8, 16: at least a portion of 180 etched back to form portions 183, 185).
Yu does not teach the method further comprising annealing the protective layer prior to etching back the protective layer.
Yu-925 teaches a method including forming a protective layer (¶ 0037: 80), annealing the protective layer (¶ 0037: repair anneal), and etching back the protective layer (¶ 0038: 80 etched back).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Yu with an anneal, as a means to repair damage (Yu-925, ¶ 0037) prior to forming source/drain cavities (210, 250 of Yu, 86 of Yu-925).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818