DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species c (claims 1-21) in the reply filed on 12/1/2025 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR STRUCTURE COMPRISING A DIAMOND BLOCK
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 6 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Gaul (US 20110140126), hereinafter Gaul.
Regarding claim 6, Gaul (US 20110140126) (refer to Figure 5) teaches a semiconductor structure (para 3-4), comprising:
a substrate (107, para 26);
a first circuit containing composite block (102, para 25) over the substrate; wherein the first circuit containing composite block comprises a first semiconductor block (16, para 10) and a first diamond block (22, para 10), the first circuit containing composite block comprises a first through via (36, para 12) therein, and a first set of IC circuit (such as BJTs, see para 11) in the first semiconductor block; and
a cold plate (109, para 26) bonded to the first circuit containing composite block.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gaul, in view of Yu (US 20140117564), hereinafter Yu.
Regarding claims 1-3 and 5, Gaul (US 20110140126) (refer to Figure 5) teaches a semiconductor structure (para 3-4), comprising:
a substrate (107, para 26); and
a first circuit containing composite block (102, para 25) over the substrate;
wherein the first circuit containing composite block comprises a through via (36 of 102, para 12) therein;
wherein the first circuit containing composite block comprises a semiconductor block (16, para 10 and a diamond block (22, para 10);
further (as recited in claim 2) comprising a second circuit containing composite block (104, para 25) under the first circuit containing composite block (102); wherein the second circuit containing composite block comprises a through via (36 of 104, para 12) therein and a re-distribution layer thereon; and wherein the second circuit containing composite block (104) comprises a semiconductor block (16, para 10) and/or a diamond block (22, para 10); and
still further (as recited in claim 3) the first circuit containing composite block or the second circuit containing composite block further comprises a plurality of IC circuits (such as BJTs and MOS devices, see para 11).
Gaul does not teach “a re-distribution layer” thereon; i.e. a re-distribution layer on the first circuit containing composite block (as recited in claim 1) and also on the second circuit containing composite block (as recited in claim 2), and that (as recited in claim 5) “the re-distribution layer comprises an electrical interconnection or an optical waveguide”. Yu (US 20140117564) (refer to Figure 1) teaches a semiconductor structure (para 17) comprising a first circuit containing composite block (100, which may be “a silicon or glass interposer” – see para 17) and a diamond block (106 of Figure 1, which may be a “dielectric” such as “CVD Black Diamond-I”, para 18), which not only comprises a through via (110, described as "Through-substrate vias 110" in para 120) therein but also a re-distribution layer (122, described as “redistribution layer 122” in para 24) thereon, wherein the re-distribution layer is electrically coupled (through 110) to other parts of the circuit. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul to further include “a re-distribution layer” thereon; i.e. a re-distribution layer on the first circuit containing composite block (as recited in claim 1) and also on the second circuit containing composite block (as recited in claim 2), and that (as recited in claim 5) “the re-distribution layer comprises an electrical interconnection or an optical waveguide”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of forming a typical interconnection structure in integrated circuits (para 2 and 6 of Yu) for providing reliable electrical interconnections (para 29 of Yu) under thermal cycling loads (para 28 of Yu) using a re-distribution layer that is electrically coupled (through 110) to other parts of the circuit.
Regarding claim 4, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 1, wherein the through via (36 of 102, para 12) is a thermal via (para 12 describes that 36 can be “used to pass heat vertically through the device”).
Regarding claim 18, Gaul (US 20110140126) (refer to Figure 5) teaches a semiconductor structure (para 3-4), comprising:
a substrate (107, para 26);
a first circuit containing composite block (102, para 25) over the substrate, wherein the first circuit containing composite block comprises a first semiconductor block (16, para 10) and a first diamond block (22, para 10), and the first circuit containing composite block comprises a first through via (36 of 102, para 12) therein, and a first set of IC circuit (such as BJTs and MOS devices, see para 11) in the first semiconductor block;
a second circuit containing composite block (104, para 25) bonded (by 38, see para 26) to the first circuit containing composite block (106); wherein the second circuit containing composite block comprises a second semiconductor block (16, para 10) and a second diamond block (22, para 10), the second circuit containing composite block comprises a second through via (36 of 104, para 12) therein, and a second set of IC circuit (such as BJTs and MOS devices, see para 11) in the second semiconductor block; and
an interposer (106, para 25) above the substrate and under the second circuit containing composite block, wherein the interposer comprises a third semiconductor block (16, para 10) and a third diamond block (22, para 10), the interposer comprises a third through via (36, para 12) therein.
Although Gaul teaches that the interposer (106) is electrically coupled (by 42 and 32 – see para 26) to the second circuit containing composite block (104) Gaul does not teach that the interposer comprises “a re-distribution layer thereon; wherein the re-distribution layer is electrically or optically coupled to the second circuit containing composite block”. Yu (US 20140117564) (refer to Figure 1) teaches a semiconductor structure (para 17) comprising an interposer comprising a semiconductor block (100, which may be “a silicon or glass interposer” – see para 17) and a diamond block (106 of Figure 1, which may be a “dielectric” such as “CVD Black Diamond-I”, para 18), further comprises a through via (110, described as "Through-substrate vias 110" in para 120) therein and a re-distribution layer (122, described as “redistribution layer 122” in para 24) thereon, wherein the re-distribution layer is electrically coupled (through 110) to other parts of the circuit. It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the interposer comprises a re-distribution layer thereon; wherein the re-distribution layer is electrically coupled to the second circuit containing composite block. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of forming a typical interconnection structure in integrated circuits (para 2 and 6 of Yu) for providing reliable electrical interconnections (para 29 of Yu) under thermal cycling loads (para 28 of Yu) using common techniques such as a redistribution layer.
Claims 7-9 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Gaul in view of Pavio (US 7582962), hereinafter Pavio.
Regarding claim 7, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 6, further comprising an interposer (106, para 25) above the substrate (107) and under the first circuit containing composite block (102), but does not teach that the interposer comprises “a fluidic via”. Pavio (US 7582962) (refer to Figure 2) teaches a semiconductor structure (101, see Col. 4, lines 3-14) wherein thermal vias (112, see Col. 4, lines 3-14) are interposed between a first circuit containing component (102, see Col. 2, lines 13-20) and a substrate (108, see Col. 2, lines 13-20), the interposed structure comprising vias (112, Col. 4, lines 3-14) and the via are fluidic via (Col. 4, lines 3-14 describes “thermal via 112” may be used “in conjunction with” a “coolant” for “further heat removal). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the interposer comprises “a fluidic via”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using fluidic vias to enhance thermal dissipation by using a cooling fluid in fluidic vias.
Regarding claim 8, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 7, further comprising a second circuit containing composite block (104, para 25) bonded to (by 38, see para 26) the first circuit containing composite block; wherein the second circuit containing composite block comprises a second semiconductor block (16, para 10) and a second diamond block (22, para 10), and the second circuit containing composite block comprises a second through via (36, para 12) therein.
Regarding claim 9, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 8, but does not teach “a diamond layer is between the cold plate and the first circuit containing composite block”. However, Gaul teaches that diamond layer provides high thermal conductivity (para 7) and Figure 5 shows how a diamond layer (22) can advantageously be placed between a circuit (16) and a heat dissipating member (109, para 26). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that additionally a diamond layer is placed he cold plate and the first circuit containing composite block. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using the high thermal conductivity material like diamond layer (as explained in para 26 of Gaul) to improve heat transfer to the cold plate.
Regarding claim 14, Gaul (refer to Figure 5) teaches a semiconductor structure (para 3-4), comprising:
a substrate (107, para 26);
a first semiconductor block (16 of 102, para 10 and 25) over the substrate, wherein the first semiconductor block comprises a first set of IC circuit (such as BJTs, see para 11);
a second semiconductor block (16 of 104, para 10 and 25) bonded to (by 38) the first semiconductor block, wherein the second semiconductor block comprises a second set of IC circuit (such as BJTs, see para 11); and
an interposer (106, para 25) above the substrate (107) and under the second semiconductor block (16 of 104),
Gaul does not teach that the interposer comprises “a fluidic via”. Pavio (refer to Figure 2) teaches a semiconductor structure (101, see Col. 4, lines 3-14) wherein thermal vias (112, see Col. 4, lines 3-14) are interposed between a first circuit containing component (102, see Col. 2, lines 13-20) and a substrate (108, see Col. 2, lines 13-20), the interposed structure comprising vias (112, Col. 4, lines 3-14) and the via are fluidic via (Col. 4, lines 3-14 describes “thermal via 112” may be used “in conjunction with” a “coolant” for “further heat removal). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the interposer comprises “a fluidic via”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using fluidic vias to enhance thermal dissipation by using a cooling fluid in fluidic vias.
Regarding claim 15, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 14, further comprising a cold plate (109, para 26) bonded to the first semiconductor block.
Regarding claim 16, Gaul (refer to Figure 5) teaches a semiconductor structure (para 3-4), comprising:
a substrate (107, para 26);
a first semiconductor block (16 of 102, para 10 and 25) over the substrate (107), wherein the first semiconductor block comprises a first set of IC circuit (such as BJTs, see para 11); and
a second semiconductor block (16 of 104, para 10 and 25) bonded to the first semiconductor block, wherein the second semiconductor block comprises a second set of IC circuit (such as BJTs, see para 11).
Gaul does not teach each of the first semiconductor block and the second semiconductor block a “fluidic channel”; i.e. first semiconductor block comprises “a first fluidic channel “and the second semiconductor block comprises “a second fluidic channel”. Pavio (refer to Figure 2) teaches a semiconductor structure (101, see Col. 4, lines 3-14) wherein thermal vias (112, see Col. 4, lines 3-14) are interposed between a first circuit containing component (102, see Col. 2, lines 13-20) and a substrate (108, see Col. 2, lines 13-20), the interposed structure comprising vias (112, Col. 4, lines 3-14) and the via are fluidic via (Col. 4, lines 3-14 describes “thermal via 112” may be used “in conjunction with” a “coolant” for “further heat removal). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that each of the first semiconductor block and the second semiconductor block a “fluidic channel”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using fluidic vias to enhance thermal dissipation for each semiconductor block by using a cooling fluid in fluidic vias.
Regarding claim 17, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 16, further comprising a cold plate (109, para 26) bonded to the first semiconductor block.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Gaul and Pavio, as applied to claim 8 above, further in view of hereinafter Bezama (US 20060260784), hereinafter Bezama.
Regarding claim 10, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 8, but does not teach further comprising “a structural member surrounding the first circuit (para 23, especially last 4 sentences) containing composite block and the second circuit containing composite block, wherein the structural member comprises a fluidic channel fluidly coupled to the fluidic via of the interposer”.
Bezama (US 20060260784) (refer to Figure 2D) teaches a semiconductor structure (para 2), further comprising a structural member (15, described as “fluid distribution structure 15” in para 39) surrounding a circuit containing block (70, described as “chip carrier 70” or “substrate 70” in para 55), wherein the structural member comprises a fluidic channel (comprising 28, 38 described as "fluid inlet microjets 28 and the outlet microjet drains 38" in para 43).
Regarding the teaching that the fluidic channel is “fluidly coupled to the fluidic via of the interposer”, Pavio (US 7582962) (refer to Figure 2) teaches a semiconductor structure (101, see Col. 4, lines 3-14) wherein thermal vias (112, see Col. 4, lines 3-14) are interposed between a first circuit containing component (102, see Col. 2, lines 13-20) and a substrate (108, see Col. 2, lines 13-20), the interposed structure comprising vias (112, Col. 4, lines 3-14) and the via are fluidic via (Col. 4, lines 3-14 describes “thermal via 112” may be used “in conjunction with” a “coolant” for “further heat removal).
It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the semiconductor structure further comprises “a structural member surrounding the first circuit (para 23, especially last 4 sentences) containing composite block and the second circuit containing composite block, wherein the structural member comprises a fluidic channel fluidly coupled to the fluidic via of the interposer”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using fluidic vias to enhance thermal dissipation by using a cooling fluid in fluidic vias, wherein the cooling fluid is controlled by a fluid distribution structure (para 39 of Bezama) that surrounds the circuits to be cooled (i.e. the first circuit containing composite block and the second circuit containing composite block) for cooling with microjets to increased thermal performance (para 43 of Bezama) of the semiconductor structure.
Regarding claim 11, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 10, but does not teach further comprising “a micro-jet coupled to” the first circuit containing composite block. Bezama (US 20060260784) teaches a semiconductor structure, further teaching that coupling a micro-jet to high power dissipating semiconductor chips is known in the art (para 2; also see para 32 and 43 in the context of Figure 2D). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the semiconductor structure further comprises “a micro-jet coupled to” the first circuit containing composite block”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of advantageously using cooling with microjets to increased thermal performance (para 43 of Bezama) of the semiconductor structure.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gaul, Pavio and Bezama, as applied to claim 10 above, and further in view of Nelson (US 20080101013), hereinafter Nelson.
Regarding claims 12-13, Gaul (refer to Figure 5) teaches the semiconductor structure in claim 10, that is designed to enhance heat transfer from the semiconductor structure (para 12 of Gaul) but does not teach further comprising “a dielectric liquid coolant filled between” the structural member and the first circuit containing composite block (as recited in claim 12); and further (as recited in claim 13), the second circuit containing composite block bonded to the first circuit containing composite block “through oxide-to-oxide bonding or polyimide (PI)-to-PI bonding”.
Nelson (US 20080101013) teaches a semiconductor structure (para 5), further disclosing the advantages of using a dielectric liquid coolant (38, para 13) filled between members that have to be cooled (such as “power devices 34” and “substrate 36” – see para 11 and Figure 1 or 2; also see para 13), wherein the substrate may be bonded to devices through oxide-to-oxide bonding (see para 11 which describes “substrate 36” may be “a direct bonded copper substrate” such as “a copper-coated aluminum oxide”). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that the semiconductor structure further comprises a dielectric liquid coolant filled between the members to be cooled; i.e. the structural member and the first circuit containing composite block (as recited in claim 12); and further (as recited in claim 13), the second circuit containing composite block is bonded to the first circuit containing composite block through a known bonding technique such as oxide-to-oxide bonding. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of providing optimal power device cooling by using “dielectric coolant” which is “most effective” (para 3 of Nelson) compare to other coolants such as water (para 2 of Nelson), and using it in conduction with a high thermal conductivity copper heat sink bonded to a substrate, such as direct a direct bonded copper substrate which uses oxide-oxide bonding (para 11 of Nelson), creating a high power semiconductor structure suitable for use onboard an electric/hybrid vehicle (para 1 of Nelson).
Claims 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Gaul and Yu, as applied to claim 18, and further in view of Chen (US 20210305227), hereinafter Chen.
Regarding claims 19-20, Gaul (US 20110140126) (refer to Figure 5) teaches the semiconductor structure in claim 18, but does not teach further comprising “a structural member surrounding” the first circuit containing composite block and the second circuit containing composite block, and further comprising “a lid joined to the semiconductor structural member”.
Chen (US 20210305227) teaches that a semiconductor structure comprising a first circuit (132, para 45 – labelled in Figure 2A) may be hermetically sealed (para 3) by including a structural member (210, see Figure 3 and para 44) surrounding the first circuit, and further comprising a lid (330, para 48 – see Figure 3) joined to the semiconductor structural member (210). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that it comprises “a structural member surrounding” the first circuit containing composite block and the second circuit containing composite block, and further comprises “a lid joined to the semiconductor structural member”. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of providing mechanical integrity and hermetic sealing from the external environment, thus improving reliability of the semiconductor structure (para 3 of Chen)
Regarding claim 21, Gaul (US 20110140126) (refer to Figure 5) teaches the semiconductor structure in claim 20, but does not teach comprising “a diamond layer between the lid and the first circuit containing composite block”.
However, Gaul teaches that diamond layer provides high thermal conductivity (para 7) and Figure 5 shows how a diamond layer (22) can advantageously be placed between a circuit (16) and a heat dissipating member (109, para 26). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Gaul so that a diamond layer is placed between the lid and the first circuit containing composite block. The ordinary artisan would have been motivated to modify Gaul for at least the purpose of using a high thermal conductivity lid (such as a metal lid) as a heat dissipating member, advantageously using the high thermal conductivity (as explained in para 26 of Gaul) of intervening diamond layer to improve heat transfer.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892