DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/4/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (20160233142) in view of Yu (20110278732)
Regarding Claim 1, in Figs. 1A-5 and paragraphs 0043, 0076 and 0077, Xu et al. discloses a method to process a diamond composite wafer 2/4/6/16, comprising:(a) forming a plurality of through vias 6 in the diamond composite wafer and a first re-distribution layer 20-1 on a first side of the diamond composite wafer;(b) attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer (Figs. 1C and 1D); (c) releasing the temporary carrier to form a circuit containing diamond composite wafer (Figs. 4, 5 6). Xu et al. fails to disclose the newly added limitation of:
“then removing a portion of the diamond composite wafer to expose a terminal surface of each of the through vias and then forming a second re-distribution layer on a second side of the diamond composite wafer”
However, such limitation is disclosed in Fig. 1, paragraphs 0018, 0029 and 0120 as elements 100/110/122.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required added above limitation in Xu et al. as taught by Yu in order to have RLD/interconnect/UBM structure on both sides of a composite substrate and electrically connect them with the usage of through via.
Regarding Claim 2, in Xu et al, the diamond composite wafer comprises a semiconductor substrate with a predetermined diameter and a plurality of diamond blocks 4 on the semiconductor substrate.
Regarding Claim 3, in Xu et al, the semiconductor substrate comprises a plurality of semiconductor blocks 10 consolidated into the predetermined diameter.
Regarding Claim 4, in Xu et al., forming a plurality of IC circuits in the semiconductor substrate (see paragraph 0077)
Regarding Claim 5, in Xu et al, the first re-distribution layer is formed on the semiconductor substrate, and the second re-distribution layer is formed on the plurality of diamond blocks (see paragraphs 0076, 0077, and 0079)
Regarding Claim 6, in Xu et al, dicing the circuit containing diamond composite wafer into a plurality of circuit containing composite block, each circuit containing composite block comprising one of the diamond blocks and a semiconductor block diced from the semiconductor substrate (see paragraph 0077(.
Regarding Claim 7, in Xu et al, each of the plurality of through vias comprises an electrical via (i.e. metal), an optical via, a thermal via and/or a fluidic via.
Regarding Claim 8, in Xu et al, the first re-distribution layer and/or the second re-distribution layer comprises an electrical interconnection or an optical waveguide (see paragraph 0076, 0077 and 0079).
Regarding Claim 9, in Figs. 1A-5 of Xu et al, the diamond composite wafer comprises a first semiconductor substrate with a predetermined diameter, a plurality of diamond blocks on the first semiconductor substrate, and a second semiconductor substrate with the predetermined diameter on the first semiconductor substrate.
Regarding Claim 10, in paragraphs 0076, 0077 and 0079 of Xu et al, the first re-distribution layer is formed on the first semiconductor substrate, and the second re-distribution layer is formed on the second semiconductor substrate.
Regarding Claim 11, in paragraph 0077 of Xu et al, dicing the circuit containing diamond composite wafer into a plurality of circuit containing composite block, each circuit containing composite block comprising one of the diamond blocks, a first semiconductor block diced from the first semiconductor substrate, and a second semiconductor block diced from the second semiconductor substrate.
Regarding Claim 12, in Figs. 1A-5 of Xu et al, the diamond composite wafer comprises a plurality of diamond blocks consolidated into a predetermined diameter.
Regarding Claim 13, in paragraph 0076, 0077 and 0079 of Xu et al, first re-distribution layer and the second re-distribution layer are formed on different sides of the plurality of diamond blocks consolidated with the predetermined diameter
Regarding Claim 14, in paragraph 0077 of Xu et al, dicing the circuit containing diamond composite wafer into a plurality of circuit containing composite block, each circuit containing composite block comprising one of the diamond blocks.
Please note that commonly owned Tong 20230154825 discloses thermal enhanced diamond structure semiconductor device and there is not joint ownership statement against Tong at this time.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/6/2026