DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II, Species A, claims 10-20, in the reply filed on 1/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 1-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/27/2026.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-11, 14, 16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 2018/0122701).
(Re Claim 10) Li teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (100; Fig. 3); forming a first source region (left 112; Fig. 3), a first drain region (right 112; Fig. 3), a second source region (left 122; Fig. 3) and a second drain region (right 122; Fig. 3) on the substrate; forming a first high-k material layer (310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (310 covering 121; Fig. 3) on the substrate, wherein the first high-k material layer is between (left to right; Fig. 3) the first source region and the first drain region, and the second high-k material layer (left to right; Fig. 3) is between the second source region and the second drain region; removing the second high-k material layer (Fig. 4); forming a third high-k material layer (330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; forming a fourth high-k material layer (330 covering 320; Fig. Fig. 8) on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region (Fig. 8); and forming a first gate layer (340+350+360+370+380 covering the first high-k material; Fig. 12) and a second gate layer (340+350+360+370+380 covering the fourth high-k material layer; Fig. 12) on the third high-k material layer and the fourth high-k material layer respectively.
(Re Claim 11) Li teaches the method according to claim 10, wherein a thickness of the first high-k material layer is approximately the same as a thickness of the second high-k material layer (Fig. 3, ¶46), and a thickness of the third high-k material layer is approximately the same as a thickness of the fourth high-k material layer (Fig. 3, ¶69).
(Re Claim 14) Li teaches the method according to claim 10, wherein the first high-k material layer and the third high-k material layer comprise the same material (¶¶123-124).
(Re Claim 16) Li teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (100; Fig. 3); forming a first source region (left 112; Fig. 3), a first drain region (right 112; Fig. 3), a second source region (left 122; Fig. 3) and a second drain region (right 122; Fig. 3) on the substrate; forming a first high-k material layer (310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer on the substrate (330 covering 320; Fig. 8), wherein the first high-k material layer is between the first source region and the first drain region (Fig. 3), and the second high-k material layer is between the second source region and the second drain region (Fig. 8); forming a third high-k material layer (330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and forming a first gate layer (340+350+360+370+380 covering the first high-k material; Fig. 12) and a second gate layer (340+350+360+370+380 covering the second high-k material; Fig. 12) on the third high-k material layer and the second high-k material layer respectively.
(Re Claim 19) Li teaches the method according to claim 16, wherein a thickness of the second high-k material layer is larger than 12 A (¶69).
(Re Claim 20) Li teaches the method according to claim 10, wherein a sum of a thickness of the first high-k material layer and a thickness of the third high-k material layer is larger than 15 A (¶¶46, 69).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12, 14-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579) and Li (US 2018/0122701).
(Re Claim 10) Lu teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (101; Fig. 5); forming a first source region (107a; Fig. 5), a first drain region (107b; Fig. 5), a second source region (108a; Fig. 5) and a second drain region (108b; Fig. 5) on the substrate; forming a first high-k material layer (part of 117 covering the left 116; Fig. 6) and a second high-k material layer (part of 117 covering the right 116; Fig. 6) on the substrate, wherein the first high-k material layer is between the first source region (Fig. 6) and the first drain region, and the second high-k material layer is between the second source region (Fig. 6) and the second drain region; and
forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14).
Lu has not been shown to teach a method comprising: removing the second high-k material layer; forming a third high-k material layer on the first high-k material layer; forming a fourth high-k material layer on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region; and
forming the first gate layer and the second gate layer on the third high-k material layer and the fourth high-k material layer respectively.
Li teaches forming a first high-k material layer (310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (310 covering 121; Fig. 3) on a substrate (100; Fig. 3);
removing the second high-k material layer (Fig. 4); forming a third high-k material layer (330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and forming a fourth high-k material layer (330 covering 320; Fig. Fig. 8) on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region (Fig. 8).
A PHOSITA would find it obvious to form and utilize the high-k dielectric material layers of Li, according to Li’s teachings, for the high-k dielectric material layers of Lu, to reduce the leakage current of the NMOS device of Lu (Lu: ¶31; Li: ¶16), while maintaining an appropriate high-k dielectric material layer thickness for the PMOS device of Lu (Li: ¶40).
This results in modified Lu teaching a method comprising:
forming a first high-k material layer (Li: 310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (Li: 310 covering 121; Fig. 3) on a substrate (Lu: 101; Fig. 5);
removing the second high-k material layer (Li: Fig. 4); forming a third high-k material layer (Li: 330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and forming a fourth high-k material layer (Li: 330 covering 320; Fig. Fig. 8) on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region (Li: Fig. 8); and
forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14) on the third high-k material layer (Lu: Fig. 14; Li: Fig. 8) and the fourth high-k material layer (Lu: Fig. 14; Li: Fig. 8) respectively.
(Re Claim 11) Modified Lu teaches the method according to claim 10, wherein a thickness of the first high-k material layer is approximately the same as a thickness of the second high-k material layer (Li: Fig. 3, ¶46), and a thickness of the third high-k material layer is approximately the same as a thickness of the fourth high-k material layer (Li: Fig. 3, ¶69).
(Re Claim 12) Modified Lu teaches the method according to claim 10, further comprising: forming a first interfacial layer (left 116; Fig. 6) on the substrate, wherein the first interfacial layer is between the first source region and the first drain region (Fig. 6); forming a second interfacial layer (right 116; Fig. 6) on the substrate, wherein the second interfacial layer is between the second source region and the second drain region (Fig. 6), wherein the first interfacial layer and the first high-k material layer comprise different materials (SiO2 versus e.g., HfO2; Li: ¶39; Lu: ¶45).
(Re Claim 14) Modified Lu teaches the method according to claim 10, wherein the first high-k material layer and the third high-k material layer comprise the same material (¶¶123-124).
(Re Claim 15) Modified Lu teaches the method according to claim 10, further comprising: performing an ion implantation process to form the first source region, the first drain region, the second source region and the second drain region (¶31), wherein the first source region and the first drain region comprise n-type dopants (¶31), and the second source region and the second drain region comprise p-type dopants (¶31).
(Re Claim 16) Lu teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (101; Fig. 5); forming a first source region (107a; Fig. 5), a first drain region (107b; Fig. 5), a second source region (108a; Fig. 5) and a second drain region (108b; Fig. 5) on the substrate; forming a first high-k material layer (part of 117 covering the left 116; Fig. 6) and a second high-k material layer on the substrate (part of 117 covering the right 116; Fig. 6), wherein the first high-k material layer is between the first source region and the first drain region (Fig. 6), and the second high-k material layer is between the second source region and the second drain region (Fig. 6); and forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14).
Lu has not been shown to teach a method comprising:
forming a third high-k material layer on the first high-k material layer; and
forming a first gate layer and a second gate layer on the third high-k material layer and the second high-k material layer respectively.
Li teaches forming a first high-k material layer (310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (330 covering 121; Fig. 8) on a substrate (100; Fig. 3); and
forming a third high-k material layer (330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and
A PHOSITA would find it obvious to form and utilize the high-k dielectric material layers of Li, according to Li’s teachings, for the high-k dielectric material layers of Lu, to reduce the leakage current of the NMOS device of Lu (Lu: ¶31; Li: ¶16), while maintaining an appropriate high-k dielectric material layer thickness for the PMOS device of Lu (Li: ¶40).
This results in modified Lu teaching a method comprising:
forming a first high-k material layer (Li: 310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (Li: 330 covering 121; Fig. 8) on a substrate (Lu: 101; Fig. 5); and
forming a third high-k material layer (Li: 330 covering the first high-k material layer; Fig. 8) on the first high-k material layer (Li: Fig. 8); and
forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14) on the third high-k material layer (Lu: Fig. 14; Li: Fig. 8) and the second high-k material layer (Lu: Fig. 14; Li: Fig. 8) respectively.
(Re Claim 17) Modified Lu teaches the method according to claim 16, further comprising: forming a first interfacial layer (left 116; Fig. 6) on the substrate, wherein the first interfacial layer is between the first source region and the first drain region (Fig. 6); forming a second interfacial layer on the substrate (right 116; Fig. 6), wherein the second interfacial layer is between the second source region and the second drain region (Fig. 6), wherein the first interfacial layer and the first high-k material layer comprise different materials (SiO2 versus e.g., HfO2; Li: ¶39; Lu: ¶45).
(Re Claim 19) Modified Lu teaches the method according to claim 16, wherein a thickness of the second high-k material layer is larger than 12 A (Li: ¶69).
(Re Claim 20) Modified Lu teaches the method according to claim 10, wherein a sum of a thickness of the first high-k material layer and a thickness of the third high-k material layer is larger than 15 A (Li: ¶¶46, 69).
Claims 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579) and Li (US 2018/0122701) as respectively applied to claims 12 and 17 above, and further in view of Lee et al. (US 2011/011/0143529).
(Re Claim 13) Modified Lu teaches the method according to claim 12, but has not been shown to teach the method wherein a thickness of the first interfacial layer is smaller than 10 A.
Lee teaches forming an interfacial layer (232; Fig. 2C) with a thickness ranging from about 3 to about 20 Angstrom (¶22).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to select a thickness for the first interfacial layer within the range provided by Lee that is smaller than 10 A, to have a reduced switching time.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 18) Modified Lu teaches the method according to claim 17, but has not been shown to teach the method wherein a thickness of the first interfacial layer is smaller than 10 A.
Lee teaches forming an interfacial layer (232; Fig. 2C) with a thickness ranging from about 3 to about 20 Angstrom (¶22).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to select a thickness for the first interfacial layer within the range provided by Lee that is smaller than 10 A, to have a reduced switching time.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rotondaro et al. (US 2005/0136632) teaches forming interfacial layers (610; Fig. 6E) and high-k dielectric layers (614, 618; Fig. 6E) according to the voltage level of the region (¶10).
Visokay et al. (US 2006/0246647) teaches forming NMOS and PMOS devices within a core region and an I/O region (Fig. 6Q-6R).
Hyun et al. (US 2008/0305620) teaches that generally NMOS devices having higher leakage current than PMOS devices (¶3).
Mo et al. (US 2010/0264495) teaches forming NMOS and PMOS devices in two different regions (Fig. 14).
Park et al. (US 2011/0121399) teaches forming spacers after forming layers of high-k dielectric material (Fig. 5).
Wang et al. (US 2011/0254093) teaches transistor structure (Fig. 11).
Tong et al. (US 8,722,485) teaches depositing both an interfacial layer (211; Fig. 5) and a high-k material layer (215; Fig. 5) such that their side edges are aligned (Fig. 5).
Gerhardt et al. (US 2014/0027859) teaches removal of conformally deposited high-k dielectric material (16; Fig. 2F, ¶31).
Song (US 2015/0236113) teaches making the sides of a high-k material layer (122; Fig. 4) and an interfacial layer (120; Fig. 5) aligned.
Zhou (US 2016/0064506) teaches forming a high-k material layer (26; Fig. 3, ¶46) only at the bottom of a trench (23; Fig. 3).
Chen et al. (US 2014/0246732) teaches properties affected by the thickness of an interfacial layer (¶20).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898