DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 10-12, 14-15, 19-20, and 24-29 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579), Li (US 2018/0122701), and Gerhardt et al. (US 2014/0027859), all of record.
(Re Claim 10) Lu teaches a method for manufacturing a semiconductor device, comprising: providing a substrate (101; Fig. 5); forming a first source region (107a; Fig. 5), a first drain region (107b; Fig. 5), a second source region (108a; Fig. 5) and a second drain region (108b; Fig. 5) on the substrate;
forming a first interfacial layer (left 116; Fig. 6) on the substrate, wherein in the first interfacial layer is between the first source region and the first drain region (Fig. 6);
forming a second interfacial layer (right 116; Fig. 6) on the substrate, wherein the second interfacial layer is between the second source region and the second drain region (Fig. 6); forming a first high-k material layer (part of 117 covering the left 116; Fig. 6) and a second high-k material layer (part of 117 covering the right 116; Fig. 6) on the substrate, wherein the first high-k material layer is between the first source region (Fig. 6) and the first drain region and directly contacts the first interfacial layer (Fig. 6), and the second high-k material layer is between the second source region (Fig. 6) and the second drain region and directly contacts the second interfacial layer (Fig. 6); and
forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14).
Lu has not been shown to teach a method comprising: removing the second high-k material layer and exposing the second interfacial layer; forming a third high-k material layer on the first high-k material layer; forming a fourth high-k material layer on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region and directly contacts the second interfacial layer; and
forming the first gate layer and the second gate layer on the third high-k material layer and the fourth high-k material layer respectively,
wherein a sum of a thickness of the first high-k material layer and a thickness of the third high-k material layer is larger than a thickness of the fourth high-k material layer.
Li teaches forming a first high-k material layer (310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (310 covering 121; Fig. 3) on a substrate (100; Fig. 3);
removing the second high-k material layer (Fig. 4); forming a third high-k material layer (330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and forming a fourth high-k material layer (330 covering 320; Fig. Fig. 8) on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region (Fig. 8).
A PHOSITA would find it obvious to form and utilize the high-k dielectric material layers of Li, according to Li’s teachings, for the high-k dielectric material layers of Lu, to reduce the leakage current of the NMOS device of Lu (Lu: ¶31; Li: ¶16), while maintaining an appropriate high-k dielectric material layer thickness for the PMOS device of Lu (Li: ¶40).
Gerhardt teaches removing a second high-k material layer (part of 16 covering 40A; Fig. 2F) and exposing a second interfacial layer (40A; Fig. 2F).
A PHOSITA would find it obvious to forming the first and second high-k material layer on the first and second interfacial layers, as the presence of the second interfacial layer during the removal of the second high-k material layer protects the underlying substrate during that removal step.
This results in modified Lu teaching a method comprising:
forming a first high-k material layer (Li: 310 at the bottom of the opening 141; Fig. 3) and a second high-k material layer (Li: 310 covering 121; Fig. 3) on a substrate (Lu: 101; Fig. 5);
removing the second high-k material layer (Li: Fig. 4) and exposing the second interfacial layer (Lu: the second high-k material layer was formed on the second interfacial layer; Gerhardt: Fig. 2F); forming a third high-k material layer (Li: 330 covering the first high-k material layer; Fig. 8) on the first high-k material layer; and forming a fourth high-k material layer (Li: 330 covering 320; Fig. Fig. 8) on the substrate, wherein the fourth high-k material layer is between the second source region and the second drain region (Li: Fig. 8); and
forming a first gate layer (1402 except 1430; Fig. 14) and a second gate layer (1404 except 1430; Fig. 14) on the third high-k material layer (Lu: Fig. 14; Li: Fig. 8) and the fourth high-k material layer (Lu: Fig. 14; Li: Fig. 8) respectively,
wherein a sum of a thickness (measured top to bottom above the middle of the first interfacial layer) of the first high-k material layer and a thickness (measured top to bottom above the middle of the first interfacial layer) of the third high-k material layer is larger than a thickness (measured top to bottom above the middle of the second interfacial layer) of the fourth high-k material layer (the first high-k material is non-zero, and the third and fourth high-k material layers have the same thickness measurement).
(Re Claim 11) Modified Lu teaches the method according to claim 10, wherein the thickness of the first high-k material layer is approximately the same as a thickness (measured from top to bottom above the middle of the second interfacial layer) of the second high-k material layer (Li: Fig. 3, ¶46), and the thickness of the third high-k material layer is approximately the same as the thickness of the fourth high-k material layer (Li: Fig. 3, ¶69).
(Re Claim 12) Modified Lu teaches the method according to claim 10, wherein the first interfacial layer and the first high-k material layer comprise different materials (SiO2 versus e.g., HfO2; Li: ¶39; Lu: ¶45).
(Re Claim 14) Modified Lu teaches the method according to claim 10, wherein the first high-k material layer and the third high-k material layer comprise the same material (¶¶123-124).
(Re Claim 15) Modified Lu teaches the method according to claim 10, further comprising: performing an ion implantation process to form the first source region, the first drain region, the second source region and the second drain region (¶31), wherein the first source region and the first drain region comprise n-type dopants (¶31), and the second source region and the second drain region comprise p-type dopants (¶31).
(Re Claim 19) Modified Lu teaches the method according to claim 10, wherein a thickness of the second high-k material layer is larger than 12 A (Li: ¶69).
(Re Claim 20) Modified Lu teaches the method according to claim 10, wherein the sum of a thickness of the first high-k material layer and the thickness of the third high-k material layer is larger than 15 A (Li: ¶¶46, 69).
(Re Claim 24) Modified Lu teaches the method according to claim 10, wherein the first high-k material layer, the second high-k material layer, the third high-k material layer, and the fourth high-k material layer independently comprise at least one of Hafnium(IV) oxide (HfO2) (Lu: the first and second high-k material layers are HfO2; ¶40; Li: the third and fourth high-k material layers are HfO2; ¶124), lanthanum(III) oxide (La2O3), and tantalum pentoxide (Ta2O5).
(Re Claim 25) Modified Lu teaches the method according to claim 10, wherein the first high-k material layer and the second high-k material layer are formed through the same deposition process (Lu: Fig. 6).
(Re Claim 26) Modified Lu teaches the method according to claim 25, wherein the third high-k material layer and the fourth high-k material layer are formed through the same deposition process (Li: Fig. 7).
(Re Claim 27) Modified Lu teaches the method according to claim 10, wherein the first high-k material layer and the third high-k material layer comprise different materials (Lu: the first high-k material layer is HfO2; ¶40; Li: the third high-k material layer is ZrO2; ¶124).
(Re Claim 28) Modified Lu teaches the method according to claim 10, wherein an etching process (using mask 230; ¶50) or a polishing process is performed to remove the second high-k material layer.
(Re Claim 29) Modified Lu teaches the method according to claim 10, further comprising forming a first well (102; Fig. 6) and a second well (103; Fig. 6) on the substrate, wherein the first source region and the first drain region are in the first well (Fig. 6), the second source region and the second drain region are in the second well (Fig. 6), wherein the first well, the first source region, the first drain region, the first interfacial layer, the first high-k material layer, the third high-k material layer, and the first gate layer form a n-type field-effect transistor structure (the preceding layers are above n-type first source 107a and drain 107b regions, and a p-type well 102; ¶¶29, 31), the second well, the second source region, the second drain region, the second interfacial layer, the fourth high-k material layer and the second gate layer form a p-type field-effect transistor structure (the preceding layers are above p-type second source 108a and drain 108b regions, and an n-type well 103; ¶¶29, 31).
Claims 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579), Li (US 2018/0122701), and Gerhardt et al. (US 2014/0027859), all of record, as respectively applied to claims 12 and 17 above, and further in view of Lee et al. (US 2011/011/0143529), of record.
(Re Claim 13) Modified Lu teaches the method according to claim 12, but has not been shown to teach the method wherein a thickness of the first interfacial layer is smaller than 10 A.
Lee teaches forming an interfacial layer (232; Fig. 2C) with a thickness ranging from about 3 to about 20 Angstrom (¶22).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to select a thickness for the first interfacial layer within the range provided by Lee that is smaller than 10 A, to have a reduced switching time.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
(Re Claim 18) Modified Lu teaches the method according to claim 10, but has not been shown to teach the method wherein a thickness of the second interfacial layer is smaller than 10 A.
Lee teaches forming an interfacial layer (232; Fig. 2C) with a thickness ranging from about 3 to about 20 Angstrom (¶22).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to select a thickness for the first interfacial layer within the range provided by Lee that is smaller than 10 A, to have a reduced switching time.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579), Li (US 2018/0122701), and Gerhardt et al. (US 2014/0027859), all of record, as applied to claim 10 above, and further in view of Lee et al. (US 2021/0035989) newly cited.
(Re Claim 21) Modified Lu teaches the method according to claim 10, but has not been explicitly shown to teach a thickness of the first interfacial layer is approximately the same as a thickness of the second interfacial layer.
Lee teaches that a thickness of a first (221; Fig. 4C) and second (121; Fig. 4C) interfacial layer may be approximately the same (¶¶41, 45).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first interfacial layer of modified Lu with a thickness (measured from top to bottom in Lu’s Fig. 6) that is approximately the same as a thickness (measured from top to bottom in Lu’s Fig. 6) of the second interfacial layer, as taught by Lee, as them the same will provide both with equivalent insulation from the substrate (Lee: ¶25).
(Re Claim 22) Modified Lu teaches the method according to claim 21, but has not been explicitly shown to teach the thickness of the first interfacial layer and the thickness of the second interfacial layer are both smaller than 10 Å.
Lee teaches that forming interfacial layers with thicknesses smaller than 10 Å prevents the degradation of device characteristics (¶25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form teach the thickness of the first interfacial layer and the thickness of the second interfacial layer are both smaller than 10 Å to prevent the degradation of device characteristics (Lee: ¶25).
(Re Claim 23) Modified Lu teaches the method according to claim 21, wherein the first interfacial layer and the second interfacial layer both comprise silicon dioxide (SiO2) (¶39).
Claims 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2013/0026579), Li (US 2018/0122701), and Gerhardt et al. (US 2014/0027859), all of record, as applied to claim 29 above, and further in view of Liaw (US 2021/0057023) newly cited.
(Re Claim 30) Modified Lu teaches the method according to claim 29, but has not been explicitly shown to teach the semiconductor device comprises memory cells, each of the memory cells includes a plurality of the n-type field-effect transistor structures and a plurality of the p-type field-effect transistor structures.
Lu does teach utilizing the transistor structures in an SRAM device (¶74), but does not specify the particular configuration of memory cells.
Liaw teaches forming a semiconductor device (400; Fig. 8) comprising memory cells (200Y+200XY; Fig. 8), each of the memory cells includes a plurality of n-type field-effect transistor structures (each pull-down transistor within each memory cell; ¶32) and a plurality of p-type field-effect transistor structures (each pull-up transistor with each memory cell; ¶32).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the n-type and p-type field-effect transistor structures of modified Lu to form a semiconductor device comprising memory cells as taught by Liaw, as the n-type and p-type transistor structures of modified Lu have improved device performance (Lu: ¶31; Li: ¶¶16, 40).
This results in modified Lu teaching the semiconductor device (Liaw: 400) comprises memory cells (200Y+200XY; Fig. 8), each of the memory cells includes a plurality of the n-type field-effect transistor structures (each pull-down transistor has a structure corresponding to the n-type field-effect transistor structure described by modified Lu) and a plurality of the p-type field-effect transistor structures (each pull-up transistor has a structure corresponding to the n-type field-effect transistor structure described by modified Lu).
(Re Claim 31) Modified Lu teaches the method according to claim 30, wherein the memory cells are memory cells of a 6T (six-transistor) static random-access memory (6T shown in Liaw’s Fig. 8), or memory cells of a 8T (eight-transistor) static random-access memory or memory cells of a 10T (ten- transistor) static random-access memory.
Response to Arguments
Applicant's arguments filed 6/11/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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