DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election of Invention I (directed to a device), Species I-1 shown in Figs. 1- 3 in the Response (filed 01/07/26) to Restriction Requirements has been acknowledged.
In the Response, Applicant cancelled method Claims 16-20 (directed to Invention II), added device Claims 21-25, and amended original Claim 15.
Applicant did not show in the Response whether Species I-1 has been chosen with or without traverse, and did not reflect any errors in the Restriction Requirements mailed 11/13/25.
Applicant wrote that Claims 1-15 and 21-25 are directed to Species I-1. However, Claim 22, citing that a first gate intersects two first-type active regions - does not belong Species I-1; it belongs to Species I-2 shown in Figs. 4-6. Claims 23-25 depend on Claim 22.
Status of Claims
Claims 22-25 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-15 and 21 are examined on merits herein.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “front-side inductor is directly above the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor” and ‘the back-side inductor is directly below the first first-type transistor, the second first-type transistor, and first second-type transistor, the second second-type transistor”, as new Claim 21 recites must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 5 recites: “the back-side inductor includes one or more conductor segments in another back-side metal layer which have a total length that is less than a total length of the one or more conductors in the front-side upper metal layer”, which is not supported by the specification of the application, teaching only relative lengths of different conductor segments either in the back-side metal layers creating a back-side inductor or in front-side metal layers creating a front-side inductor, while not comparing lengths of conductor segments in back-side metal layers with length of front-side conductor segments.
Claim 21 recites: “a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor; a back-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor”. However, the specification of the application and original Claims 1-20 do(es) not support a disposition of any inductor directly either above or under four transistors; the specification teaches (paragraph 0056 of the published application US 2024/0290779) that each inductor (a front-side inductor or a back-side inductor) is formed directly over (or under) a stack of only two transistors.
The amendment filed 01/07/26 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Claim 21 states: “a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor; a back-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor”. However, the specification of the application and any of original Claims 1-20 do(es) not support a disposition of any inductor either above or under four transistors, it teaches (paragraph 0056 of the published application US 2024/0290779) that each inductor (a front-side inductor or a back-side inductor) is formed directly over (or under) a stack of only two transistors. Accordingly, the limitations related to direct dispositions of the front-side and back-side inductors over four transistors represent a new matter.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 21 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains a subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
In re Claim 21: Claim 21 filed 01/07/26 (about two and a half years later than the original application) has following limitations: “a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor; a back-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor”. However, the specification of the original application (filed 08/09/23) and the original claims 1-20 do not support a disposition of any inductor directly above or under four transistors, it teaches (paragraph 0056 of the published application US 2024/0290779) that each inductor (a front-side inductor or a back-side inductor) is formed directly over (or under) a stack of two transistors. Accordingly, the cited limitations of Claim 21 related to disposition each inductor either above four transistors or under four transistors represent new matter. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 21 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 5: Claim 5 recites: “the back-side inductor includes one or more conductor segments in another back-side metal layer which have a total length that is less than a total length of the one or more conductors in the front-side upper metal layer”. The recitation is unclear, since it is not supported by the specification teaching only relative lengths of different conductor segments in the back-side metal layers creating a back-side inductor, or in front-side metal layers of a front-side inductor, while not comparing lengths of back-side conductors of a back-side inductor with front-side conductors of a front-side inductor – see paragraph 0054 of the published application.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, however, the cited recitation was interpreted as filed.
In re Claim 21: Claim 21 has following limitations: “a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor; a back-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor, the second first-type transistor, the first second-type transistor, the second second-type transistor”. The recitations are unclear when they recite direct dispositions of the inductors above/below four transistors, since such dispositions conflict with the specification of the original application (and the original Claims 1-20), teaching only direct disposition of an inductor above/below (depending on the inductor type) of a stack of two transistors (see paragraph 0056 of the published application US 2024/0290779).
. In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation was interpreted in accordance with paragraph 0056 of the published application as: “a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor and the first second-type transistor; a back-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor and the first second-type transistor”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as Claim 21 is understood, Claims 1, 2, 4, 6, 9-10, 13-14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Roithmeier (US 2013/0135057) in view of Lilak et al. (US 2020/0235134) and Uchida et al. (US 2019/0393148).
In re Claim 1, Roithmeier teaches an integrated circuit device comprising (Fig. 2):
a first-type transistor NMOS-left and a second-type transistor PMOS-left (paragraph 0033);
a first inductor 28b (paragraph 0019);
a second inductor 28a (paragraph 0019); and
a capacitive element 30 (paragraph 0019) coupled to a drain terminal of the first-type transistor NMOS-left and a drain terminal of the second-type transistor PMOS-left and forming an LC oscillator 20 (paragraph 0033) with the first inductor and the second inductor.
Roithmeier teaches only electrical circuit of the device, not a structure, and, as such, he does not teach a substrate, does not teach that the first-type transistor and the second-type transistor are stacked with each other on a front side of the substrate, wherein the second-type transistor is between the first-type transistor and the substrate, does not teach that the first inductor is a front-side inductor having one or more conductors in a front-side upper metal layer above both the first-type transistor and the second-type transistor, does not teach that the second inductor is a back-side inductor having one or more conductors in a back-side lower metal layer at a back side of the substrate, wherein the front-side inductor, the first-type transistor, and the second-type transistor form a stack directly above the back-side inductor.
Lilak teaches an integrated circuit device (Figs. 23, 24, and 25) comprised a substrate 2302 (in Fig. 23, or 2502 in Fig. 25, paragraphs 0077, 0098) having a front side (as a top side) and a back side (as a bottom side), a stack of two transistors 2301 (Fig. 23, paragraph 0085) is disposed on the front side of the substrate 2302, one transistor being disposed between another transistor and the substrate, where details of a stack of transistors 104 and 102 - on a substrate – is shown in Fig. 1 and some following figures (paragraph 0020 and some other paragraphs, pointing out formation of stacks from different semiconductor materials, paragraph 0027, allowing to create one transistor of a stack as an n-type and a stacked transistor – as a p-type transistor – as used in a CMOS circuits, paragraphs 0018). Lilak further teaches that the integrated circuit has passive components, such as capacitors and inductors, that can be disposed either on the front side of the substrate or on the back side of the substrate (paragraph 0097).
Uchida teaches an integrated circuit comprised a plurality of metal layers, a front-side inductor L (Fig. 1, paragraph 0043) formed in a front-side upper metal layer M5 (paragraph 0063) above a first type transistor NM1 and a second type transistor PM1 (that are formed under the metal layers, paragraph 0043), the inductor occupying an area significantly larger than that of the transistors and larger than a half of an integrated circuit part comprised the transistors (at least in a cross-sectional view), where a circuit diagram of the Uchida device (shown in Fig. 27) is similar to the circuit diagram of Roithmeier. Although Uchida does not explicitly describe that the inductor comprises a plurality of conductors/segments, it is known in the art that a single layer inductor shown in a cross-section of Fig. 1 of Uchida as having multiple parts in metal layer M5, is created from a plurality of conductors being a spiral coil – see Figs. 3A-3B and paragraph 0010 of Wei et al. (US 2009/0072942, where a cross-section of Fig. 3A is similar to an inductor of Fig. 1 of Uchida) for the common knowledge in the art.
Roithmeier, Lilak, and Uchida teach analogous arts directed to integrated circuits comprised transistors and passive elements, such as capacitors and inductors, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in creation a structure for the Roithmeier device in view of structures of Lilak and Uchida devices, since they all are from the same field of endeavor, and Lilak and Uchida created devices that successfully operates.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create a structure for the Roithmeier device by creating first-type and second-type transistors stacked with each other at a front side of a chosen substrate, wherein the second-type transistor is between the first-type transistor and the substrate (per Lilak), wherein it is desirable not only create a structure for the disclosed circuit of the device, but also to reduce an area of the integrated circuit occupied by the first-type and second-type transistors by disposing these transistors in the stack.
It would have been further obvious for one of ordinary skill in the art before filing the application to further modify the structure of the integrated circuit device (per Uchida) by creating a plurality of metal layers over the front surface of the substrate, when such structure is desirable, and to incorporate one inductor of Roithmeier as a front-side inductor (per Uchida) into the front-side upper metal layer above the stack of the first-type and second-type transistors (based on Lilak and Uchida), if such modification is desirable and in order to create the first front-side inductor needed for the Roithmeier device. It would have been further obvious to create a capacitive element of the Roithmeier, coupled to drain terminals of the first-type and second-type of transistors, either above the front side of the substrate or under the back side of the substrate (per Lilak) enabling by that the integrated circuit c omprised the first inductor and the capacitive element.
Since the Uchida inductor is two large in comparison with other elements, and a second inductor of Roithmeier (if created of the same size) would not fit in the remaining space of the integrated circuit, it would have been obvious for one of ordinary skill in the art before filing the application to create the second inductor needed for the Roithmeier circuit as a back-side inductor (per Lilak) mirroring the front-side inductor but at the back surface of the substrate (since it is easy to repeat a structure of one inductor on another surface of the substrate), creating for that a plurality of metal layers from the back side of the substrate and disposing the back-side inductor in the lowest metal layer as a spiral coil and under the stack of the first-type and second-type transistors, creating by that a structure, where the front-side inductor and the stack of the first-type and second-type transistors form a stack directly above the back-side inductor.
It would have been further obvious for one of ordinary skill in the art before filing the application to create the capacitive element coupled to the drains of the first-type and second-type transistors either as a front-side capacitor or a back-side capacitor (per Lilak), enabling the capacitive part of the Roithmeier device.
In re Claim 2, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, creating the first inductor as the front-side inductor and the second inductor as the back-side inductor.
Roithmeir further teaches (Fig. 2) that the front-side inductor and the back-side inductor are connected in series.
In re Claim 4, Roithmeir/Lilak/Uchida the integrated circuit device of Claim 1 as cited above, wherein, as explained for Claim 1 (in Uchida) the front-side inductor is a
spiral coil in the front-side upper metal layer.
In re Claim 6, Roithmeir/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, wherein, as explained for Claim 1, the back-side inductor is a spiral coil in the back-side lower metal layer.
In re Claim 9, Roithmeier teaches an integrated circuit device comprising:
a first-type transistor NMOS – shown as Mn-left (Fig. 2, paragraph 0033);
a second-type transistor PMOS – shown as Mp-left (Fig. 2, paragraph 0033);
a first inductor 28b (paragraph 0019);
a second inductor 28a (paragraph 0019), wherein
the first inductor 28b and the second inductor 28a are conductively connected in series and forms a combined inductor which has a first terminal conductively connected to a drain terminal of the first-type transistor Mn-left or a drain terminal of the second-type transistor Mp-left – the combined inductor first terminal is conductively connected to both - the drain terminal of the first-type transistor and the second-type, as shown in Fig. 2.
Roithmeier teaches only a circuit diagram of the device, and, accordingly, does not teach: a substrate; a first-type active-region semiconductor structure and a second-type active-region semiconductor structure stacked with each other at a front side of the substrate, the first-type transistor formed with the first-type active-region semiconductor structure, the second-type transistor formed with the second-type active region semiconductor structure, a plurality of front-side middle conductive layers above both the first-type active-region semiconductor structure and the second-type active-region semiconductor structure at the front side of the substrate; a front-side upper metal layer above the plurality of front-side middle conductive layers; the first inductor being a front-type inductor having one or more conductors in the front-side upper metal layer; a back-side lower metal layer at a back side of the substrate; the second inductor being a back-type inductor having one or more conductors in the back-side lower metal layer.
Lilak teaches an integrated circuit device (Figs. 23, 24, and 25) comprised a substrate 2302 (in Fig. 23, or 2502 in Fig. 25, paragraphs 0077, 0098) having a front side (as a top side) and a back side (as a bottom side), a stack of two transistors 2301 (Fig. 23, paragraph 0085) disposed on the front side of the substrate 2302, one transistor being disposed between another transistor and the substrate, where details of transistors stacks are shown in Fig. 1 describing a substrate 106 (paragraph 0020), a first type active region – with fins 114 (paragraph 0021 and the first transistors 110 formed with the first type active region, a second type active region - with fins 138 (paragraphs 0027) and the second transistors 136 formed with the second type active regions (paragraph 0027), where the first and second type active regions may include different semiconductor materials (paragraph 0027), and, accordingly, may be incorporated into transistors of different conductivity types, respectively (as appropriate for a CMOS structure, paragraph 0018). Lilak further teaches that the integrated circuit has passive components, such as capacitors and inductors, that can be disposed either on the front side of the substrate or on the back side of the substrate (paragraph 0097).
Uchida teaches an integrated circuit comprised a plurality of metal layers formed over transistors and further comprised a front-side inductor L (Fig. 1, paragraph 0043) formed in a front-side upper metal layer M5 (paragraph 0063) above a first type transistor NM1 and a second type transistor PM1 (paragraph 0043), the front-side inductor occupying an area significantly larger than that of the transistors and larger than a half of the integrated circuit (at least in a cross-sectional view), where a circuit diagram of the Uchida device (shown in Fig. 27) is similar to the circuit diagram of Roithmeier. Although Uchida does not explicitly describe that the front-side inductor comprises a plurality of conductors/segments, it is known in the art that a single layer inductor shown in a cross-section of Fig. 1 of Uchida as having multiple parts in metal layer M5, is created from a plurality of conductors being a spiral coil – see Figs. 3A-3B and paragraph 0010 of Wei et al. (US 2009/0072942, where a cross-section of Fig. 3A is similar to an inductor of Fig. 1 of Uchida) for the common knowledge in the art.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create a structure for the Roithmeier circuit by creating the stacked with each other first-type and second-type active layer over a substrate, the first-type active layer for the first-type transistor and the second active layer for the second-type of transistor stacked with each other at a front side of the substrate (per Lilak), wherein it is desirable not only create a structure for the disclosed circuit of the device, but also to reduce an area of the integrated circuit occupied by the first-type and second-type transistors by creating these transistors in the stack.
It would have been further obvious for one of ordinary skill in the art before filing the application to further modify the structure of the integrated circuit device (per Uchida) by creating a plurality of metal layers over the front surface of the substrate the transistors (including a plurality of front-side middle conductive layers) and to incorporate one inductor of Roithmeier as a front-side inductor (per Uchida) in the front-side upper metal layer above the stack of the first-type and second-type transistors (per Uchida), when it is desirable to have an integrated circuit with a plurality of front metal layers and the first front-side inductor needed for the Roithmeier device. It would have been further obvious to create a capacitive element of the Roithmeier, coupled to drain terminals of the first-type and second-type of transistors, either above the front side of the substrate or under the substrate (per Lilak) enabling by that the integrated circuit comprised the stack of transistors, the first inductor, and the capacitive element.
Since the Uchida inductor is two large in comparison with other elements, and the second inductor of Roithmeier (if created with the size of the first inductor) would not fit in the remaining space of the integrated circuit, it would have been obvious for one of ordinary skill in the art before filing the application to create the second inductor needed for the Roithmeier circuit as a back-side inductor (per Lilak) mirroring the front-side inductor but at the back surface of the substrate (since it is easy to repeat a structure of one inductor on another surface of the substrate), creating for that a plurality of metal layers from the back side of the substrate and further, vertically, under the back surface of the substrate, and disposing the back-side inductor in the lowest metal layer as a spiral coil and under the stack of the first-type and second-type transistors, creating by that a structure, where the front-side inductor and the stack of the first-type and second-type transistors form a stack directly above the back-side inductor.
It would have been further obvious for one of ordinary skill in the art before filing the application to create the front-side and back-side inductors in series (as in the Roithmeier circuit) and conductively connected to a first terminal, which is connected to a drain terminal of the first-type transistor and/or the second-type transistor (per Roithmeier’ circuit).
In re Claim 10, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 9 as cited above, wherein, as is clear from Fig. 2 of Roithmeier, the first terminal of the combined inductor is conductively connected to both the drain terminal of the first-type transistor and the drain terminal of the second-type transistor.
In re Claim 13, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 9 as cited above, including the stack of the PMOS transistor and the NMOS transistor.
Since it does not matter for the structure, the first-type transistor could be created as the PMOS transistor, and the second-type transistor could be created as the NMOS transistor.
In re Claim 14, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 9 as cited above, including the stack of the PMOS transistor and the NMOS transistor.
Since it does not matter for the structure, the first-type transistor could be created as the NMOS transistor, and the second-type transistor could be created as the PMOS transistor.
In re Claim 21, Roithmeier teaches an integrated circuit device comprising:
a first first-type transistor NMOS – shown as Mn-left (Fig. 2, paragraph 0033);
a second first-type transistor MNOS – shown as Mn-right (Fig. 2, paragraph 0033)
a first second-type transistor PMOS – shown as Mp-left (Fig. 2, paragraph 0033);
a second second-type transistor PMOS – shown as MP-right (Fig. 2, paragraph 0033)
a first inductor 28b (paragraph 0019);
a second inductor 28a (paragraph 0019), wherein
the first inductor 28b and the second inductor 28a are conductively connected in series and forms a combined inductor, wherein a first terminal of the combined inductor is conductively connected to a drain terminal of the first first-type transistor Mn-left and a drain terminal of the first second-type transistor Mp-left, and wherein a second terminal of the combined inductor is conductively connected to a drain terminal of the second first-tupe transistor MN-right and a drain terminal of the second second-type transistor Mp-right.
Roithmeier teaches only a circuit diagram of the device, and, accordingly, does not teach: a substrate; a first-type active-region semiconductor structure and a first second-type active-region semiconductor structure stacked with each other at a front side of the substrate, a second first-type active region semiconductor structure and a second second-type active semiconductor structure stacked with each other at the front side of the substrate, where the first-type transistor is formed with the first first-type active region semiconductor structure, the second first-type transistor formed with the second first-type active region structure, the first second-type transistor formed with the first second-type active region semiconductor structure, and the second second-type transistor is formed with the second second-type active region semiconductor structure. Roithmeier further does not teach that the first inductor is a front-side inductor dominantly formed with conductors in a front-side upper metal layer, wherein the front-side inductor is directly above the first first-type transistor, the second first=type transistor, the first second-type transistor and the second second-type transistor.
Roithmeier also does not teach that the second inductor is a bck-side inductor dominantly formed with conductors in a back-side lower metal layer at a back side of the substrate, wherein the back-side inductor is directly below the first first-type transistor, the second first-type transistor, the first second-type transistor, and the second second-type transistor.
Lilak teaches an integrated circuit device (Figs. 23, 24, and 25) comprised a substrate 2302 (in Fig. 23, or 2502 in Fig. 25, paragraphs 0077, 0098) having a front side (as a top side) and a back side (as a bottom side), a stack of two transistors 2301 (Fig. 23, paragraph 0085) disposed on the front side of the substrate 2302, where details of the transistors stack are shown in Fig. 1 describing a substrate 106 (paragraph 0020), a first type active region – with fins 114 (paragraph 0021 and the first transistors 110 formed with the first type active region, a second type active region - with fins 138 (paragraphs 0027) and the second transistors 136 formed with the second type active regions (paragraph 0027), where the first and second type active regions may include different semiconductor materials (paragraph 0027), and, accordingly, these different active regions may be incorporated into a stack of transistors of different conductivity types, respectively (as appropriate for a CMOS structure, paragraph 0018). Lilak further teaches that the integrated circuit has passive components, such as capacitors and inductors, that can be disposed either on the front side of the substrate or on the back side of the substrate (paragraph 0097).
Uchida teaches an integrated circuit comprised a plurality of metal layers formed over a plurality of transistors (PM1, PM2, NM1, and NM2) and further comprised a front-side inductor L (Fig. 1, paragraph 0043) formed in a front-side upper metal layer M5 (paragraph 0063) above a first first-type transistor NM1 and a first second-type transistor PM1 (paragraph 0043), the front-side inductor L occupying an area significantly larger than that of the transistors and larger than a half of the integrated circuit (at least in a cross-sectional view), where a circuit diagram of the Uchida device (shown in Fig. 27) is similar to the circuit diagram of Roithmeier. Although Uchida does not explicitly describe that the front-side inductor comprises a plurality of conductors/segments, it is known in the art that a single layer inductor shown in a cross-section of Fig. 1 of Uchida as having multiple parts in metal layer M5, is formed from a plurality of conductors creating a spiral coil – see Figs. 3A-3B and paragraph 0010 of Wei et al. (US 2009/0072942, where a cross-section of Fig. 3A is similar to an inductor of Fig. 1 of Uchida) for the common knowledge in the art.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to form a structure for the Roithmeier circuit by creating stacked with each other first first-type and first second-type active layers (with corresponding transistors) at the front side of the substrate, as well as stacked with each other second first-type active layer and second second-type active layer (with corresponding transistors) at the front side of the substrate (per Lilak), wherein it is desirable not only to create a structure for the disclosed Roithmeier circuit of the device, but also to reduce an area of the integrated circuit occupied by the four transistors by creating pairs these transistors in the stack.
It would have been further obvious for one of ordinary skill in the art before filing the application to further modify the structure of the integrated circuit device (per Uchida) by creating a plurality of metal layers over the front surface of the substrate the transistors (including a plurality of front-side middle conductive layers) and to incorporate one inductor of Roithmeier as a front-side inductor (per Uchida) in the front-side upper metal layer above the stack of the first first-type and first second-type transistors (per Lilak and Uchida) and the stack of the second first-type transistor and the second second-type transistor (as interpreted) when it is desirable to have an integrated circuit with a plurality of front metal layers and the first front-side inductor needed for the Roithmeier device.
Since the Uchida inductor is two large in comparison with transistors, and the second inductor of Roithmeier (if created with the size of the first inductor) would not fit in the remaining space of the integrated circuit, it would have been obvious for one of ordinary skill in the art before filing the application to create the second inductor needed for the Roithmeier circuit as a back-side inductor (per Lilak) mirroring the front-side structure and the front-side inductor but at the back surface of the substrate (since it is easy to repeat a structure of one inductor on another surface of the substrate), creating for that a plurality of metal layers from the back side of the substrate and further, vertically, under the back surface of the substrate, and disposing the back-side inductor in the lowest metal layer as a spiral coil and under the stacks of transistors (as interpreted), creating by that a structure, where the front-side inductor and two stacks of the transistors (as interpreted) directly above the back-side inductor.
It would have been further obvious for one of ordinary skill in the art before filing the application to create the front-side and back-side inductors in series (as in the Roithmeier circuit) and conductively connected to a first terminal, which is connected to a drain terminal of the first-type transistor and/or the second-type transistor (per Roithmeier’ circuit). Since each of the front-side and back-side inductors are created in a single metal layer, they inherently are dominantly formed in the corresponding layer.
As far as Claim 5 is understood, Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Roithmeier/Lilak/Uchida in view of Dong (US 2020/0005980).
In re Claim 3, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, including the single-layer inductor of Uchida.
Uchida does teach that the front-side inductor includes one or more conductor segments in another front-side metal layer which have a total length that is less than a total length of the one or more conductors in the front-side upper metal layer, wherein the one or more conductors in the front-side upper metal layer are conductively connected in series by the one or more conductor segments.
Dong teaches an inductor (Fig. 2, paragraphs 0020-0021) that includes a few conductor segments in metal layer M1 and a few conductor segments in metal layer M2, each conductor segment in both layers is serially either with laterally adjacent segments, or with one laterally adjacent segment and a segment in another layer, where a total length of conductors in layer M2 is less than a total length of conductors in layer M1.
Roithmeier/Lilak/Uchida and Dong teach analogous arts directed to spiral inductors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Roithmeier/Lilak/Uchida device in view of the Dong device, since they are from the same field of endeavor, and Dong created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device by substituting the Uchida front-side inductor disposed in a single metal layer with an inductor of Dong disposed in two metal layers, such as in the upper metal layer (per Uchida) and an adjacent another metal layer (per Dong), where one or more conductor segments in another front-side metal layer have a total length that is less than a total length of the one or more conductors in the front-side upper metal layer, if such type of the front-side inductor is preferred for the manufacturer. Note that a disposition of the inductor side with the longest total length of the conductors in the upper metal layer is a designer choice, while a substitution of one element with a similar element performing the same function is a matter of obviousness: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 5, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, including the back-side inductor formed in the back-side lower metal layer, similar to the front-side inductor, but on the back side of the substrate.
Roithmeier/Lilak/Uchida does not teach that the back-side inductor includes one or more conductor segments in another back-side metal layer which have a total length that is less than a total length of the one or more conductors in the front-side upper metal layer, wherein the one or more conductors in the back-side lower metal layer are conductively connected in series by the one or more conductor segments.
Dong teaches an inductor (Fig. 2, paragraphs 0020-0021) that includes a few conductor segments in metal layer M1 and a few conductor segments in metal layer M2, each conductor segment in both layers is serially either with laterally adjacent segments, or with one laterally adjacent segment and a segment in another layer, where a total length of conductors in layer M2 is less than a total length of conductors in layer M1.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device by substituting the back-side inductor disposed in a single metal layer with an inductor of Dong disposed in two metal layers, such as in the back-side metal layer (as in Claim 1) and in an adjacent another metal layer (per Dong), where one or more conductor segments in another back-side metal layer have a total length that is less than a total length of the one or more conductors in the back-side lower metal layer, if such type of the back-side inductor is preferred for the manufacturer. Note that a disposition of the inductor side with the longest total length of the conductors in the lower metal layer is a designer choice, while a substitution of one element with a similar element performing the same function is a matter of obviousness: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Where the first and second inductors of Roithmeier, 28a and 28b (Fig. 2) have a same inductance (and Roithmeier does not state that the inductances are different while shows two inductors with a same number of turns), it would have been obvious for one of ordinary skill in the art before filing the application to create the total length of the front-side inductor being larger than a total length of the one or more conductors in the another back-side metal layer of the back-side inductor, in order to preserve the total inductance of the back-side inductor, also having conductors in the lower back-side metal layer (as shown for Claim 1): based on the known expression for inductance of the coil inductor – it is proportional to a number of turns and a radius of a turn.
Claims 7-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Roithmeier/Lilak/Uchida in view of Felnhofer et al. (US 2013/0100065).
In re Claim 7, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, including the capacitive element, which is a varactor of the Roithmeier circuit (e.g., “adjustable capacitor”, paragraph 0019) created over the front surface of the substrate, per Lilak.
Roithmeier/Lilak/Uchida does not teach that the capacitive element is in
one or more front-side middle conductive layers between the substrate and the front-side upper metal layer, but Uchida teaches a pluralities of non-occupied metal layers between the front-side upper metal layer (in which a large front-side inductor is disposed) and the substrate.
Felnhofer teaches (Fig. 9, paragraphs 0073-0074) a varactor having its first and second electrodes 904 and 914 created in a two vertically separated metal layers, respectively.
Roithmeier/Lilak/Uchida and Felnhofer teach analogous arts directed to varactors, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Roithmeier/Lilak/Uchida device in view of the Felnhofer device, since they are from the same field of application, and Felnhofer created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device of Claim 1 by disposing the varactor of Roithmeier, based on the integrated circuit structure of Claim 1 comprised a plurality of non-occupied metal layers between the upper front metal layer (with the large front-side inductor) and the substrate and based on the varactor structure of Felnhofer - between the upper front-sde metal layer and the substrate, in order to enable a disposition of the capacitive structure of the integrated circuit.
In re Claim 8, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 1 as cited above, wherein the capacitive element of Roithmeier is a varactor (e.g., “adjustable capacitor”, paragraph 0019), which can be disposed under the back-side surface of the substrate, per Lilak.
Roithmeier/Lilak/Uchida does not teach that the capacitive element is created in
one or more back-side middle conductive layers between the substrate and the back-side lower metal layer. However, similar to a front-side of the Uchida device, the integrated circuit of Claim 1 has a plurality of non-occupied back-side metal layers disposed between the lower metal layer (in which the large back-side inductor is disposed) and the back-side of the substrate.
Felnhofer teaches (Fig. 9, paragraphs 0073-0074) a varactor having its first and second electrodes 904 and 914 in two vertically separated metal layers, respectively.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device of Claim 1 by disposing the varactor of Roithmeier, based on the integrated circuit structure of Claim 1 comprised a plurality of non-occupied metal layers between the lower backside metal layer and the substrate and based on the varactor structure of Felnhofer - in a few back-side middle conductive layers between the lower back-side metal layer and the substrate, in order to enable a disposition of the capacitive structure of the integrated circuit.
In re Claim 11, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 9 as cited above and comprising a capacitive element formed over the front surface of the substrate (per Lilak). Since Roithmeier teaches that his capacitor element 30 (Fig. 2, and being a varactor, e.g., “adjustable capacitor”, paragraph 0019) is connected to the drain terminal of the first-type transistor Mn and to the drain terminal oc the second-type transistor Mp, it would have been obvious for one of ordinary skill in the art before the filing date of the application to connect the capacitor terminal of Claim 9 per Roithmeier.
Roithmeier/Lilak/Uchida does not teach that the capacitive element is formed in the plurality of front-side middle conductive layers, but Uchida teaches a pluralities of non-occupied middle metal layers between the front-side upper metal layer (in which a large front-side inductor is disposed) and the substrate.
Felnhofer teaches (Fig. 9, paragraphs 0073-0074) a varactor having its first and second electrodes 904 and 914 created in a two vertically separated metal layers, respectively.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device of Claim 9 by disposing the capacitive element (varactor) of Roithmeier within a plurality of non-occupied middle metal layers of the structure of Claim 9, in order to enable a disposition of the capacitive structure of the integrated circuit.
In re Claim 12, Roithmeier/Lilak/Uchida teaches the integrated circuit device of Claim 9 as cited above, wherein the capacitive element of Roithmeier is a varactor (e.g., “adjustable capacitor”, paragraph 0019), which can be disposed under the back-side surface of the substrate, per Lilak, wherein, as shown for Claim 9, the plurality of back-side metal lines (incorporating middle back-side metal lines) includes the lowest back metal incorporating the back-side inductor, and wherein the plurality of back-side middle metal layers, similar to the plurality of front-side middle metal layers are not connected to any structure (since they are created mirroring the metal layers of the front structure).
Since Roithmeier teaches (Fig. 2) the capacitive element being conductively connected to the drain terminal of the first-type transistor and the drain terminal of the secocnd0type transistor, it would have been obvious for one of ordinary skill in the art before filing the application also creating this connection in the structure of Claim 9.
Roithmeier/Lilak/Uchida does not teach the capacitive element is formed in the plurality of back-side middle conductive layers.
Felnhofer teaches (Fig. 9, paragraphs 0073-0074) a varactor having its first and second electrodes 904 and 914 in two vertically separated metal layers, respectively.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Roithmeier/Lilak/Uchida device of Claim 9 by disposing the varactor of Roithmeier, based on the integrated circuit structure of Claim 9, comprised a plurality of non-occupied metal layers between the lower backside metal layer and the substrate and based on the varactor structure of Felnhofer - in a few back-side middle conductive layers between the lower back-side metal layer and the substrate, in order to enable a disposition of the capacitive structure of the integrated circuit.
Allowable Subject Matter
Claim 15 is objected to as being dependent on the rejected Claim 9, but would be allowed if amended to incorporate all limitations of claim 9.
Reason for Indicating Allowable Subject Matter
Re Claim 15: The prior arts of record do(es) not anticipate and do(es) not render obvious such limitations of Claim 15 as: “a first (second) gate-conductor intersecting the first-type (second-type) semiconductor structure at a channel region”, “a first terminal-conductor intersecting the first-type active-region semiconductor structure at a drain region”, and “a varactor having the second gate-conductor as a first terminal and the second terminal-conductor as a second terminal”, in combination with other limitations of Claim 15 and with all limitations of Claim 9, on which Claim 9 depends.
The prior arts of record, in addition to the prior arts cited by the current Office Action, also include: Yemenicioglu et al. (US2023/0420512), Cheng et al. (US 12/279,452), and O’brein et al. (US 2023/0113614).
Conclusion
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 01/27/26