DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. C laim 10 recites “ wherein the gate structure comprises a gate-all-around structure ”. Claim 10 is dependent of claim 1 which recites “a superlattice structure disposed on the fin base structure” (line 7 of claim 1). A superlattice structure, as normally used in the art, refers to a stack of at least two material layers arranged in alternating manner. Since claim 1 defines the superlattice structure to be different than the gate structure, the superlattice cannot include any material of the gate structure. The only structure in the specification of the instant application that would meet this limitation would be the structure in Fig. 14, i.e. the dummy polysilicon gate structure is still present and cover the superlattice structure. However, this dummy gate is not a gate-all-around structure. Only the final metal gate structure is a gate-all-around structure, as shown in Fig. 17 of the specification. However, the structure in Fig. 17 would not meet the “superlattice structure” of the claim 1. Thus, it is unclear whether the applicant is intended to claim the intermediate structure of Fig. 14 or the final structure of Fig. 17. For the purpose of examination, if the gate is on the side, it is interpreted to be sufficient for “gate-all-around structure”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1 -2, 4- 7, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 9318553 B1) in view of Ching et al. (US 2017/0005195 A1) and Beasom et al. (US 5780311) . Regarding claim 1 , Ch e ng teaches a semiconductor device ( device in Fig. 2f of Ch e ng with the dummy gate structure as described in column 4 lines 30-36 of Cheng ) , comprising: a substrate ( 2 10a ) ; a base structure ( 210b - 210c in Fig. 2a ) , comprising: an isolation structure ( buried oxide layer 210b ) disposed on the substrate; a semiconductor layer ( thin silicon layer 210c ) disposed on the isolation structure ; a superlattice structure ( nanowire stack 225 in Fig. 2a ) ; a source/drain (S/D) region ( 270 in Fig. 2f ) disposed adjacent to the superlattice structure; and a gate structure ( dummy gate 250 ) disposed on the superlattice structure. But Ch e ng does not teach that the base structure is a fin base structure, the isolation structure is a bi-layer isolation structure, and that fin base structure comprising: a channel isolation layer disposed on the semiconductor layer ; and the superlattice structure is disposed on the fin base structure . Ch i ng teaches a method of forming a nanowire device ( Figs. 2- 19 of Ching ) . The method comprises: forming a fin base structure ( lower portion of fin 202 up to oxidized layer 502 in Fig. 5 of Ching ) which includes: a channel isolation structure ( 502 ) on a fin structure; a nanowire stack ( 302 ) of alternating semiconductor layers ( 304 and 306 ) directly on the isolation structure ( as shown in Figs. 4-5 of Ching ); forming a dummy gate structure ( 902 in Fig. 9 ) on the nanowire stacks; forming source/drain struct ures ( 1302 in Fig. 13 ) adjacent the dummy gate structure; forming an ILD ( 1402 ) covering the S/D structures; removing the dummy gate structure ( see Fig. 14 ) and one of the alternating semiconductor layers in the nanowire stack ( as implied in Fig. 18 of Ching ); forming the final metal gate structure ( 1606 in Fig. 17 of Ching ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel isolation structure 502 of Ching in Cheng’s device and to have performed the replacement gate process in order to improve the device performance ( 502 serves as a diffusion barrier to APT dopants, see [0107] of Ching ) and to protect the S/D region from damage. As incorporated, the oxidized layer 502 of Ching would be formed directly under the bottommost layer of the nanowire stack of Cheng, i.e. it would be formed between layer 210c and bottommost layer 230 in Fig. 2a of Cheng . This oxidized layer 502 is identified as the channel isolation layer in the claim. The structure of Cheng-Ching at the moment after the source/drain regions are formed but before the dummy gate structure is formed is identified as the semiconductor device in the claim. But Cheng in view of Ching does not teach that the isolation structure is a bi-layer isolation structure. Bea som teaches a method of forming a SOI substrate ( Figs. 1a-1d of Beasom ). The method comprises: forming a device layer on a device wafer ( top substrate in Fig. 1a of Beasom ); forming a thermal oxide layer on top surfaces of the device layer and the handle wafer ( see Fig. 1a of Beasom ); pressing the wafers together and annealing them at 1100°C to bond the two wafers together ( Fig. 1b of Beasom ); removing the device wafer leaving the device layer on top of the handle wafer ( see Fig. 1c ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the SOI of Ch e ng -Ching as according to Beasom since this is a well-known method of forming an SOI substrate with high quality oxide ( see column 1 lines 65 to column 2 line 4 of Beasom ). As incorporated, the superlattice structure , or stack of alternating semiconductor layers, of Cheng is formed on a sacrificial wafer (device wafer in Fig. 1a of Beasom) . T he n two thermal oxide layers are formed on surface of the stack and of the handle wafer; and finally these two oxide layers are brought in contact and fused by an annealing process. Afterward, the sacrificial wafer (device wafer) is removed. The two oxide layer becomes the buried oxide layer. In other words, the buried oxide layer would be a bi-layer isolation structure. Regarding claim 2 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and also teaches wherein the bi-layer isolation structure comprises: a first dielectric layer ( lower oxide layer in Fig. 1a of Beasom, which is on the handle wafer ) disposed on the substrate, wherein the first dielectric layer comprises an oxide of a material of the substrate ( as taught in Beasom ) ; and a second dielectric layer ( upper oxide layer on the device epilayer ) disposed on the first dielectric layer, wherein the second dielectric layer comprises an oxide of a material of the semiconductor layer ( as combined in claim 1 above ) . Regarding claim 4 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and also teaches wherein the S/D region is disposed on and in contact with the channel isolation layer ( as shown in Fig. 13 of Ching and Fig. 2f of Cheng ) . Regarding claim 5 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and also teaches wherein a sidewall of the S/D region is in contact with a sidewall of the channel isolation layer ( as shown in Fig. 2f of Cheng, the S/D recess extends to the top surface of the semiconductor layer 210c of Cheng. This would mean a portion of the channel isolation layer 502 of Ching in the S/D regions would be removed to expose the top surface of the semiconductor layer 210c . As a result, a sidewall of the portion of the channel isolation layer 502 under the channel would be exposed and in contact with the epitaxial S/D regions 270 of Cheng ) . Regarding claim 6 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and also teaches wherein the S/D region is disposed on and in contact with the semiconductor layer ( as shown in Fig. 2f of Cheng ) . Regarding claim 7 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and also teaches wherein the channel isolation layer is disposed on a first portion ( portion of 210c directly under the gate in Fig. 2f of Cheng ) of the semiconductor layer; and wherein the S/D region is disposed on and in contact with a second portion ( portion of 210c in contact with epitaxial S/D regions 270 of Cheng ) of the semiconductor layer. Regarding claim 9 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, and further comprising a contact structure disposed in the fin base structure and on the S/D region ( the S/D contact structures are inherent structure of a device in order for the device to function as intended ) . Regarding claim 10 Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1 and also teaches wherein the gate structure comprises a gate-all-around structure ( as shown in Fig. 18 of Ching ) . Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ching and Beasom, as applied to claim 1 above, and further in view of Pogge (US 5681775) and Wu et al. (US 2004/0000268 A1) . Regarding claim 8 , Cheng-Ching-Beasom teaches all limitations of the semiconductor device of claim 1, but does not teach wherein the semiconductor layer comprises a germanium layer or a silicon germanium layer . Pogge teaches a method of forming an SOI substrate ( Figs. 6A- E of Pogge ). The method includes: forming a p+ semiconductor etch stop layer ( 210 in Fig. 6A ); forming thermal oxide layers ( 240 & 260 ) on top surfaces of the handle substrate ( 200 in Fig. 6B ) and carrier substrate ( 250 in Fig. 6B ); bringing the oxide layers in contact and performing a high temperature anneal to bonding the substrate; removing the handle substrate and the etch stop layer using CMP processes ( see Figs. 6D-6E of Pogge ). Wu discloses that alloying Si with a moderate Ge concentration, of about 20 to 50 atm % of Ge, leads to excellent selectivity for an etch-stop material ( see Abstract of Wu ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a p+ SiGe etch stop layer as disclosed by Pogge and Wu in order to have better control over the removal of the handle substrate in Cheng-Ching-Beasom’s method. As incorporated, the etch-stop layer 210 is epitaxially deposited on the handle substrate ( column 5 lines 65-66 of Pogge ) between the superlattice and the handle substrate (sacrificial substrate of the claim). Claims 1 1 , 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ching . Regarding claim 11 , Cheng teaches a semiconductor device ( device in Fig. 2f of Cheng with the dummy gate structure as described in column 4 lines 30-36 of Cheng ) , comprising: a substrate ( 210a ) ; an isolation structure ( buried oxide layer 210b ) disposed on the substrate; a semiconductor layer ( thin silicon layer 210c ) disposed on the isolation structure; a nanostructured channel region ( nanowires 220 in Fig. 2e ) ; a gate structure ( gate 250 ) surrounding the nanostructured channel region; and a source/drain (S/D) region ( 270 ) disposed adjacent to the nanostructured channel region. But Cheng does not teach that the semiconductor device comprises: a channel isolation layer disposed on the semiconductor layer; and the nanostructured channel region is disposed on the channel isolation layer . Ching teaches a method of forming a nanowire device ( Figs. 2-19 of Ching ). The method comprises: forming a fin base structure ( lower portion of fin 202 up to oxidized layer 502 in Fig. 5 of Ching ) which includes: a channel isolation structure ( 502 ) on a fin structure; a nanowire stack ( 302 ) of alternating semiconductor layers ( 304 and 306 ) directly on the isolation structure ( as shown in Figs. 4-5 of Ching ); forming a dummy gate structure ( 902 in Fig. 9 ) on the nanowire stacks; forming source/drain structures ( 1302 in Fig. 13 ) adjacent the dummy gate structure; forming an ILD ( 1402 ) covering the S/D structures; removing the dummy gate structure ( see Fig. 14 ) and one of the alternating semiconductor layers in the nanowire stack ( as implied in Fig. 18 of Ching ); forming the final metal gate structure ( 1606 in Fig. 17 of Ching ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel isolation structure 502 of Ching in Cheng’s device in order to improve the device performance ( 502 serves as a diffusion barrier to APT dopants, see [0107] of Ching ). As incorporated, the oxidized layer 502 of Ching would be formed directly under the bottommost layer of the nanowire stack of Cheng, i.e. it would be formed between layer 210c and bottommost layer 230 in Fig. 2a of Cheng. This oxidized layer 502 is identified as the channel isolation layer in the claim. Regarding claim 14 , Cheng in view of Ching teaches all limitations of t he semiconductor device of claim 11, and also teaches wherein the S/D region is disposed on and in contact with the semiconductor layer ( as shown in Fig. 2f of Cheng ) . Regarding claim 15 , Cheng in view of Ching teaches all limitations of t he semiconductor device of claim 11, and also teaches wherein the channel isolation layer is disposed on a first portion ( portion of 210c directly under the gate in Fig. 2f of Cheng ) of the semiconductor layer; and wherein the S/D region is disposed on and in contact with a second portion ( portion of 210c in contact with epitaxial S/D regions 270 of Cheng ) of the semiconductor layer. Claim 1 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ching, as applied to claim 11 above, and further in view of Beasom. Regarding claim 12 , Cheng in view of Ching teaches all limitations of t he semiconductor device of claim 11, but does not teach wherein the isolation structure comprises: a first dielectric layer disposed on the substrate, wherein the first dielectric layer comprises an oxide of a material of the substrate; and a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises an oxide of a material of the semiconductor layer. Bea som teaches a method of forming a SOI substrate ( Figs. 1a-1d of Beasom ). The method comprises: forming a device layer on a device wafer ( top substrate in Fig. 1a of Beasom ); forming a thermal oxide layer on top surfaces of the device layer and the handle wafer ( see Fig. 1a of Beasom ); pressing the wafers together and annealing them at 1100°C to bond the two wafers together ( Fig. 1b of Beasom ); removing the device wafer leaving the device layer on top of the handle wafer ( see Fig. 1c ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the SOI of Ch eng-Ching as according to Beasom since this is a well-known method of forming an SOI substrate with high quality oxide ( see column 1 lines 65 to column 2 line 4 of Beasom ). As incorporated, the superlattice structure , or stack of alternating semiconductor layers, of Cheng is formed on a sacrificial wafer (device wafer in Fig. 1a of Beasom) . T he n two thermal oxide layers are formed on surface of the stack and of the handle wafer; and finally these two oxide layers are brought in contact and fused by an annealing process. Afterward, the sacrificial wafer (device wafer) is removed. The two oxide layer becomes the buried oxide layer. In other words, the buried oxide layer would be a bi-layer isolation structure. Claim 1 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Ching, as applied to claim 11 above, and further in view of Rachmady et al. (US 2013/0341704 A1). Regarding claim 16 , Cheng in view of Ching teaches all limitations of t he semiconductor device of claim 11, but does not teach the semiconductor device further comprising a silicide layer disposed on the S/D region and on the channel isolation layer. Rachmady teaches a nanowire device that includes source/drain contacts ( 148 in Fig. 1B of Rachmady ) have silicide layer ( see [0032] of Rachmady ) disposed on the S/D region . Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the silicide layer on the S/D region in order to increase the conductivity of the contacts to the S/D regions. As incorporated, since the S/D region is on the semiconductor layer, the silicide layer is also on the semiconductor layer. Claims 1 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Pogge , Wu, and Ching. Regarding claim 17 , Cheng teaches a semiconductor device ( device in Fig. 2f of Cheng with the dummy gate structure as described in column 4 lines 30-36 of Cheng ) , comprising: a substrate ( 2 10a ) ; an isolation structure ( buried oxide layer 210b ) disposed on the substrate; a first nanostructured layer ( nanowire 2 3 0 ) disposed on the dielectric layer; a second nanostructured layer ( nanowire 2 2 0 ) disposed on the first nanostructured layer; a gate structure ( 250 ) disposed on the second nanostructured layer; and a source/drain (S/D) region ( 270 ) disposed on the dielectric layer. But Cheng does not teach that the semiconductor device comprising: a silicon germanium layer disposed on the isolation structure; a dielectric layer disposed on the silicon germanium layer. Pogge teaches a method of forming an SOI substrate ( Figs. 6A- E of Pogge ). The method includes: forming a p+ semiconductor etch stop layer ( 210 in Fig. 6A ); forming thermal oxide layers ( 240 & 260 ) on top surfaces of the handle substrate ( 200 in Fig. 6B ) and carrier substrate ( 250 in Fig. 6B ); bringing the oxide layers in contact and performing a high temperature anneal to bonding the substrate; removing the handle substrate and the etch stop layer using CMP processes ( see Figs. 6D-6E of Pogge ). Wu discloses that alloying Si with a moderate Ge concentration, of about 20 to 50 atm % of Ge, leads to excellent selectivity for an etch-stop material ( see Abstract of Wu ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a p+ SiGe etch stop layer as disclosed by Pogge and Wu in order to have better control over the removal of the handle substrate in Cheng device . As incorporated, the etch-stop layer 210 is epitaxially deposited on the handle substrate ( column 5 lines 65-66 of Pogge ) between the superlattice and the handle substrate (sacrificial substrate of the claim). But Cheng-Pogge-Wu does not teach that the semiconductor device comprising: a dielectric layer disposed on the silicon germanium layer. Ching teaches a method of forming a nanowire device ( Figs. 2-19 of Ching ). The method comprises: forming a fin base structure ( lower portion of fin 202 up to oxidized layer 502 in Fig. 5 of Ching ) which includes: a channel isolation structure ( 502 ) on a fin structure; a nanowire stack ( 302 ) of alternating semiconductor layers ( 304 and 306 ) directly on the isolation structure ( as shown in Figs. 4-5 of Ching ); forming a dummy gate structure ( 902 in Fig. 9 ) on the nanowire stacks; forming source/drain structures ( 1302 in Fig. 13 ) adjacent the dummy gate structure; forming an ILD ( 1402 ) covering the S/D structures; removing the dummy gate structure ( see Fig. 14 ) and one of the alternating semiconductor layers in the nanowire stack ( as implied in Fig. 18 of Ching ); forming the final metal gate structure ( 1606 in Fig. 17 of Ching ). Therefore, i t would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the channel isolation structure 502 of Ching in Cheng’s device and to have performed the replacement gate process in order to improve the device performance ( 502 serves as a diffusion barrier to APT dopants, see [0107] of Ching ) and to protect the S/D region from damage . As incorporated, the oxidized layer 502 of Ching would be formed directly under the bottommost layer of the nanowire stack of Cheng, i.e. it would be formed between layer 210c and bottommost layer 230 in Fig. 2a of Cheng. This oxidized layer 502 is identified as the channel isolation layer in the claim. The structure of Cheng-Ching at the moment after the source/drain regions are formed but before the dummy gate structure is formed is identified as the semiconductor device in the claim. Regarding claim 18 , Cheng-Pogge-Wu-Ching teaches all limitations of t he semiconductor device of claim 17, and also teaches wherein the isolation structure comprises an oxide of the silicon germanium layer ( as combined in claim 17 above, the oxidation of the layer 502 of Ching would have converted some of the SiGe layer at the interface into oxide as well. So the isolation structure would include some SiGeOx ) . Regarding claim 19 , Cheng-Pogge-Wu-Ching teaches all limitations of t he semiconductor device of claim 17, and also teaches wherein the isolation structure comprises an oxide of a material of the substrate ( silicon is a material of the substrate ) . Regarding claim 20 , Cheng-Pogge-Wu-Ching teaches all limitations of t he semiconductor device of claim 17, and also teaches wherein the first and second nanostructured layers comprise semiconductor materials different from each other ( 230 and 220 of Cheng are different materials, as stated in column 3 lines 44-55 of Cheng ) . Allowable Subject Matter Claim s 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3 , Cheng-Ching-Beasom teaches all limitations of t he semiconductor device of claim 1, wherein the channel isolation layer comprises a high-k dielectric layer. Regarding claim 13 , Cheng in view of Ching teaches all limitations of t he semiconductor device of claim 11, wherein the channel isolation layer comprises a high-k dielectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT TUAN A HOANG whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0406 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 8-9am, 10am-6pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jessica Manno can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-2339 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Tuan A Hoang/ Primary Examiner, Art Unit 2898