DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 7/14/2026 is acknowledged. Claims 1, 11-17, 19-20 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw et al. (US 2019/0109193 A1) in view of Han et al. (US 9196725 B2).
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Regarding claim 1, Liaw teaches a method (method of forming array 300 in Figs. 4A-4C of Liaw), comprising:
forming first (“fin1” in the reproduced Fig. 4A of Liaw. Fin1 extends into the dummy area 392) and second (fin 2 as labeled in the reproduced Fig. 4A of Liaw) fin structures on a substrate;
forming first and second source/drain (S/D) regions (340 as described in [0050] of Liaw) on the first and second fin structures, respectively;
forming a first polysilicon structure (the dummy gate structure over the p-well 316 in the dummy area 392 described in [0029]. This dummy gate structure is labeled as gate 1) on the first fin structure and non-overlapping with the second active structure (as shown in Fig. 4A);
forming a second polysilicon structure (the dummy gate structure over n-well 314 in the dummy area 392 described in [0029]. This dummy gate structure is labeled as gate 2) on the second fin structure and non-overlapping with the first fin structure (as shown in Fig. 4A);
depositing an interlayer dielectric (ILD) layer (352 described in [0050] of Liaw; this is analogous to 54 in Fig. 1B of Liaw) on a region (boundary region between n-well 314 and p-well 316 in the dummy area 392) of the substrate that is between the first and second polysilicon structures (as shown in Fig. 4A of Liaw, there is a gap between the first and second polysilicon structures and the ILD 352 is filled in this gap).
But Liaw does not teach the method comprising: replacing the first polysilicon structure and a first portion of the second polysilicon structure with a first metal layer; polishing the first metal layer at a first polishing rate; replacing a second portion of the second polysilicon structure with a second metal layer that is different from the first metal layer; and polishing the second metal layer at a second polishing rate that is different from the first polishing rate.
Han teaches a method (Figs. 4-13 of Han), comprising: forming first and second active regions (110 and 120 in Fig. 4 of Han) on a substrate (100); forming first (portion of dummy gate structure 140 over the active region 110) and second polysilicon structures (portion of dummy gate structure 140 over the active region 120 and the STI 130 in Fig. 6-7 of Han) on the first and second fin structures, respectively; replacing the first polysilicon structure and a first portion (portion of the dummy gate 140 over the STI 130) of the second polysilicon structure with a first metal layer (as shown in Figs. 10-11 of Han, the portion of dummy gate 140 over the STI 130 are removed and replaced with the first metal gate 175); polishing the first metal layer at a first polishing rate (column 7, lines 6-9 of Han); replacing a second portion (portion of the dummy gate 140 directly over the active region 120 in Figs. 12-13) of the second polysilicon structure with a second metal layer (185 in Fig. 13) that is different from the first metal layer; and polishing the second metal layer (as implied by the flat level of the top surfaces of 175 and 185 in Fig. 13 of Han) at a second polishing rate that is different from the first polishing rate (as stated in column 9, lines 14-17 of Han, the material of 182 and 172 are different, so it is inherent that they have different polishing rate).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Han’s gate replacement method to replace the dummy gate structure of Liaw, i.e. replacing the polysilicon gate structure with appropriate n-type/p-type metals in order to optimize the performance of the transistors.
As incorporated, all the polysilicon dummy gates of the transistors over the n-well would be replaced by the same n-type metal and all the polysilicon dummy gates of the transistors over the p-well would be replaced by the same p-type metal. As such, in the dummy area 392 in Fig. 4A of Liaw, the first polysilicon structure (gate 1 of Liaw) is replaced with p-metal gate structure. On the other hand, the second polysilicon structure (gate 2 of Liaw) has two portions - the first polysilicon portion overlaps the p-well, and the second polysilicon portion overlaps the n-well. This structure is similar to the structures in Figs. 7-13 of Han. As a result, the first polysilicon structure and the first portion of the second polysilicon structure would be replaced with the p-metal gate structure while the second portion of the second polysilicon structure would be replaced with the n-metal gate structure. Since the n-type metal and p-type metal are different (column 9 lines 14-17 of Han), their respective polishing rates would be different.
Regarding claim 2, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises forming a masking layer (160 in Fig. 10 of Han) on a top surface of the second portion of the second polysilicon structure.
Regarding claim 3, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises depositing a dielectric layer (171 in Fig. 11 of Han) on the first and second fin structures and along a sidewall of the second portion of the second polysilicon structure (as shown in Fig. 11 of Han).
Regarding claim 4, Liaw in view of Han teaches all limitations of the method of claim 3, and also teaches wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure further comprises depositing the first metal layer (175 in Fig. 11 of Han) on the dielectric layer (as shown in Fig. 11 of Han).
Regarding claim 5, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein forming the first and second fin structures comprises forming the first and second fin structures substantially parallel to each other (as shown in Fig. 4A of Liaw).
Regarding claim 6, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein forming the first and second polysilicon structures comprises forming the first and second polysilicon structures substantially parallel to each other (as shown in Fig. 4A of Liaw).
Regarding claim 7, Liaw in view of Han teaches all limitations of the method of claim 1, and further comprising forming a third fin structure (fin 3 as labeled in the reproduced Fig. 4A of Liaw) on the substrate and substantially parallel to the first and second fin structures, wherein the second portion of the second polysilicon structure is formed on the third fin structure (as shown in Fig. 4 of Liaw).
Regarding claim 8, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein replacing the second portion of the second polysilicon structure comprises depositing a dielectric layer (181 in Fig. 13 of Han) along a sidewall of the first metal layer.
Regarding claim 9, Liaw in view of Han teaches all limitations of the method of claim 8, and also teaches wherein replacing the second portion of the second polysilicon structure further comprises depositing the second metal layer on the dielectric layer (as combined in claim 1 above).
Regarding claim 10, Liaw in view of Han teaches all limitations of the method of claim 1, and also teaches wherein replacing the first polysilicon structure and the first portion of the second polysilicon structure comprises performing an oxidation process (column 6 lines 37-45 of Han) on the first and second fin structures.
Regarding claim 11, Liaw teaches a method (method of forming array 300 in Figs. 4A-4C of Liaw), comprising:
forming first (fin 1 as labeled in the Fig. 4A of Liaw reproduced below), second (fin 2), third (fin 3), and fourth fin (fin 4) structures on a substrate;
forming a first polysilicon structure (the dummy gate structure over the p-well 316 in the dummy area 392 described in [0029]. This dummy gate structure is labeled as gate 1) on the first fin structure;
forming a second polysilicon structure (the dummy gate structure labeled as gate 2) on the second fin structure;
forming a third polysilicon structure (the dummy gate structure labeled as gate 3) comprising a first polysilicon portion (portion of the dummy gate structure 3 over the fin 3) on the third fin structure and a second polysilicon portion (portion of the dummy gate structure 3 over the fin 4) on the fourth fin structure;
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replacing the first polysilicon structure with a first gate structure (the metal gate 1 that replaces the dummy gate 1);
replacing the second polysilicon structure with a third gate structure (the metal gate 3 that replaces the dummy gate 2) after replacing the first polysilicon portion;
But Liaw does not teach that the method comprising: replacing, at a same time as replacing the first polysilicon structure, the first polysilicon portion with a second gate structure; and replacing, at a same time as replacing the second polysilicon structure, the second polysilicon portion with a fourth gate structure.
Han teaches a method (Figs. 4-13 of Han), comprising: forming first and second active regions (110 and 120 in Fig. 4 of Han) on a substrate (100); forming first (portion of dummy gate structure 140 over the active region 110) and second polysilicon structures (portion of dummy gate structure 140 over the active region 120 and the STI 130 in Fig. 6-7 of Han) on the first and second fin structures, respectively; replacing the first polysilicon structure and a first portion (portion of the dummy gate 140 over the STI 130) of the second polysilicon structure with a first metal layer (as shown in Figs. 10-11 of Han, the portion of dummy gate 140 over the STI 130 are removed and replaced with the first metal gate 175); polishing the first metal layer at a first polishing rate (column 7, lines 6-9 of Han); replacing a second portion (portion of the dummy gate 140 directly over the active region 120 in Figs. 12-13) of the second polysilicon structure with a second metal layer (185 in Fig. 13) that is different from the first metal layer; and polishing the second metal layer (as implied by the flat level of the top surfaces of 175 and 185 in Fig. 13 of Han) at a second polishing rate that is different from the first polishing rate (as stated in column 9, lines 14-17 of Han, the material of 182 and 172 are different, so it is inherent that they have different polishing rate).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Han’s gate replacement method to replace the dummy gate structure of Liaw, i.e. replacing the polysilicon gate structure with appropriate n-type/p-type metals in order to optimize the performance of the transistors.
As incorporated, all the polysilicon dummy gates of the transistors over the n-well would be replaced by the same n-type metal in the same step and all the polysilicon dummy gates of the transistors over the p-well would be replaced by the same p-type metal in the same step. Since the first polysilicon portion of the third polysilicon structure (dummy gate 3 of Liaw) is over the third fin structure, which is in the p-well, this first polysilicon portion would be replaced by a third gate structure, a p-metal gate structure, in the same step with the formation of the first gate structure. Similarly, the second polysilicon portion of the third polysilicon structure is over the fourth fin structure, which is in the n-well, this second polysilicon portion would be replaced by a fourth gate structure, an n-metal gate structure, in the same step with formation of the second gate structure.
Regarding claim 12, Liaw in view of Han teaches all limitations of the method of claim 11, and also teaches wherein forming the first, second, third, and fourth fin structures comprises forming the first, second, third, and fourth fin structures substantially parallel to each other (as shown in Fig. 4A of Liaw).
Regarding claim 13, Liaw in view of Han teaches all limitations of the method of claim 11, and further comprising depositing a dielectric layer (352 described in [0050] of Liaw; this is analogous to 54 in Fig. 1B of Liaw) on regions of the substrate that are between the first, second, and third polysilicon structures, wherein forming the first, second, and third polysilicon structures comprises forming the first, second, and third polysilicon structures substantially parallel to each other and separated from each other by portions of the dielectric layer (as shown in Fig. 4A of Liaw).
Regarding claim 14, Liaw in view of Han teaches all limitations of the method of claim 11, and also teaches wherein replacing the first polysilicon portion comprises depositing a gate dielectric layer (171 in Fig. 11 of Han, as combined in claim 11 above) of the second gate structure on the third fin structure and along a sidewall of the second polysilicon portion (as shown in Fig. 11 of Han).
Regarding claim 15, Liaw in view of Han teaches all limitations of the method of claim 11, and also teaches wherein replacing the second polysilicon portion comprises depositing a gate dielectric layer (181 in Fig. 13 of Han) of the fourth gate structure on the fourth fin structure and along a sidewall of the second gate structure (as shown in Fig. 11 of Han).
Regarding claim 16, Liaw in view of Han teaches all limitations of the method of claim 11, and also teaches wherein replacing the first polysilicon portion comprises forming a masking layer (160 in Fig. 10 of Han) on the second polysilicon portion and the second polysilicon structure.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Han and Hsieh et al. (US 10157746 B2).
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Regarding claim 17, Liaw teaches a method (method of forming array 300 in Figs. 4A-4C of Liaw), comprising:
forming first and second n-type source/drain (S/D) regions (S/D structures 340, described in [0050] of Liaw, of the n-type finfet over fin 1, as labeled in the reproduced Fig. 4A above) in a substrate (312 in Figs. 4A-4C);
forming first and second p-type S/D regions (S/D structures 340 of the p-type finfet over fin 2, as described in [0050] of Liaw) disposed in the substrate;
forming a polysilicon structure (the dummy gate structure across both n-well 314 and p-well 316 in the dummy area 392 labeled in the reproduced Fig. 4A above, and as described in [0029]) comprising a first polysilicon portion (portion of the polysilicon dummy gate over the fin 1) between the first and second n-type S/D regions and a second polysilicon portion (portion of the polysilicon dummy gate over the fin 2) between the first and second p-type S/D regions.
But Liaw does not teach that the method comprising: removing the first polysilicon portion to expose a first top surface of the substrate; oxidizing the first top surface of the substrate to form a first oxide layer; depositing a first gate metal layer on the first oxide layer to form a first gate structure; removing the second polysilicon portion to expose a second top surface of the substrate; oxidizing the second top surface of the substrate to form a second oxide layer; and depositing, on the second oxide layer, a second gate metal layer different from the first gate metal layer to form a second gate structure.
Han teaches a method (Figs. 4-13 of Han), comprising: forming first (portion of dummy gate structure 140 over the active region 110) and second polysilicon structures (portion of dummy gate structure 140 over the active region 120 in Fig. 6-7 of Han) on the first and second fin structures, respectively; removing the polysilicon structures to expose top surfaces of the substrate (see Figs. 10 and 12 of Han); replacing the polysilicon with metal gate structures (175 and 185 in Figs. 11 and 13 of Han).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Han’s gate replacement method to replace the dummy gate structure of Liaw, i.e. replacing the polysilicon gate structure with appropriate n-type/p-type metals in order to optimize the performance of the transistors.
As incorporated, all the polysilicon dummy gates of the transistors over the n-well would be replaced by the same n-type metal gate and all the polysilicon dummy gates of the transistors over the p-well would be replaced by the same p-type metal gate. As such, in the dummy area 392 in Fig. 4A of Liaw, the first polysilicon portion would be replaced with n-metal gate structure and the second polysilicon portion would be replaced with a p-metal gate structure. Since the n-type metal and p-type metal are different (column 9 lines 14-17 of Han), their respective polishing rates would be different.
But Liaw in view of Han does not teach that the method comprising: oxidizing the first top surface of the substrate to form a first oxide layer; the first gate metal layer is deposited on the first oxide layer to form the first gate structure; oxidizing the second top surface of the substrate to form a second oxide layer; and depositing, on the second oxide layer, the second gate metal layer different from the first gate metal layer to form the second gate structure.
Hsieh teaches a method of forming a metal gate structure (Figs. 6D of Hsieh). The method comprises: removing the dummy gate structure (110 in Fig. 4D) to expose the top surface of the fin structure (see Fig. 5C); oxidizing the top surface of the fin to form an oxide layer (interfacial layer 132 in Fig. 6D, as described in column 5 lines 15-30 of Hsieh); forming a high-k gate dielectric layer (134 in Fig. 6D) on the oxide layer; forming a gate metal layer (140 in Fig. 6D) on the high-k gate dielectric layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed interfacial oxide layer 132 of Hsieh before forming the high-k gate dielectric layer in order to obtain a higher quality high-k dielectric layer.
Regarding claim 18, Liaw-Han-Hsieh teaches all limitations of the method of claim 17, and also teaches wherein replacing the first polysilicon portion comprises forming a masking layer (160 in Fig. 10 of Han) on the second polysilicon portion.
Regarding claim 19, Liaw-Han-Hsieh teaches all limitations of the method of claim 17, and further comprising depositing a gate dielectric layer (171 in Fig. 11 of Han, which is analogous to 134 in Fig. 6D of Hsieh) on the first oxide layer and along a sidewall of the second polysilicon portion prior to depositing the first gate metal layer.
Regarding claim 20, Liaw-Han-Hsieh teaches all limitations of the method of claim 17, and further comprising depositing a gate dielectric layer (181 in Fig. 11 of Han, which is analogous to 134 in Fig. 6D of Hsieh) on the second oxide layer and along a sidewall of the first gate structure prior to depositing the second gate metal layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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