Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 04/20/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 1, 10, and 17 that the combination of Zhou and Lee prior art, does not teach the limitation of “wherein the forming the front side circuit comprises forming buried conductive wirings disposed in an isolation insulating layer,
the front side circuit includes fin field effect transistors (FinFETs), and
the buried conductive wirings are formed between fin structures of the FinFETs.”
In response to this argument, the Examiner directs the applicant’s attention to the combination of Zhou and Lee prior art, which clearly teaches that wherein the forming the front side circuit (102) comprises forming buried conductive wirings (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive wirings”) disposed in an isolation insulating layer (see Zhou, Fig.7 as shown below),
the front side circuit (102) includes fin field effect transistors (FinFETs) (note: a front side circuit 102 is a non-planar transistor which is the fin is formed between isolation insulating layer and known to be considered as a fin field effect transistors (FinFETs)) (see Zhou, Fig.7 as shown below), and
the buried conductive wirings (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive wirings”) are formed between fin structures of the FinFETs (note: the protruding region of the substrate 100 is equivalent to the claimed limitation of “fin structures of the FinFETs”) (see Zhou, Fig.7 as shown below).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Zhou and Lee prior art reference does meet all the limitation in claims 1, 10, and 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. 2019/0273119 A1, hereinafter refer to Zhou) in view of Lee et al. (U.S. 2015/0364425 A1, hereinafter refer to Lee).
Regarding Claim 1: Zhou discloses a method of manufacturing a semiconductor device (see Zhou, Figs.6 and 7 as shown below and ¶ [0001]), comprising:
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forming a front side circuit (108/102) at a front side of a main substrate (100) (see Zhou, Figs.6 and 7 as shown above),
wherein the forming the front side circuit (102) comprises forming buried conductive wirings (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive wirings”) disposed in an isolation insulating layer (see Zhou, Fig.7 as shown above),
the front side circuit (102) includes fin field effect transistors (FinFETs) (note: a front side circuit 102 is a non-planar transistor which is the fin is formed between isolation insulating layer and known to be considered as a fin field effect transistors (FinFETs)) (see Zhou, Fig.7 as shown above), and
the buried conductive wirings (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive wirings”) are formed between fin structures of the FinFETs (note: the protruding region of the substrate 100 is equivalent to the claimed limitation of “fin structures of the FinFETs”) (see Zhou, Fig.7 as shown above);
forming through-silicon-vias (TSVs) (200) passing through the main substrate (100) to be connected to the front side circuit (108/102) (see Zhou, Figs.6 and 7 as shown above);
forming back side power supply wirings including a first back side power supply wiring and a second back side power supply wiring (see Zhou, Figs.6 and 7 as shown above);
forming a first interlayer dielectric (ILD) layer (114 bottom portion) over the back side power supply wirings (see Zhou, Figs.6 and 7 as shown above);
forming thin film transistors (TFTs) (118) over the first ILD layers (114 bottom portion) to switch power supply between the first back side power supply wiring and the second back side power supply wiring (see Zhou, Figs.6 and 7 as shown above);
forming a second ILD layer (114 top portion) over the TFTs (118) (see Zhou, Figs.6 and 7 as shown above); and
forming electrodes (112) to be connected to outside and additional wirings (see Zhou, Figs.6 and 7 as shown above).
Zhou is silent upon explicitly disclosing wherein attaching a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit.
For support see Lee, which teaches wherein attaching a sacrificial substrate (200) with a bonding layer (208) to a the front side of the main substrate (100) over the front side circuit (see Lee, Figs.1-3, 14, and 20 as shown below and ¶ [0024]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou and Lee to enable to attach a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit of Zhou as taught by Lee in order to protect the front side circuit from damage during subsequent processing steps.
Regarding Claim 5: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 1 as above. The combination of Zhou and Lee further teaches wherein one or more of the TSVs (200) are formed to be connected to one or more of the buried conductive wirings (a portion of TSV 200) (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 6: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 5 as above. The combination of Zhou and Lee further teaches wherein one or more of the TSVs (200) are connected to other circuit elements of the front side circuit (108/102) than the buried conductive wirings (a portion of TSV 200) (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 7: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 1 as above. The combination of Zhou and Lee further teaches wherein before forming the TSVs (142), reducing a thickness of the main substrate (100) at the back side of the main substrate (100) (see Lee, Figs.1-3 as shown above and ¶ [0024]).
Regarding Claim 8: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 1 as above. The combination of Zhou and Lee further teaches wherein the thin film transistors (118) are formed by:
forming a semiconductor layer (150) over the first ILD layer (114 bottom portion) (see Zhou, Figs.6 and 7 as shown above);
forming gate structures (158) over the semiconductor layer (150) (see Zhou, Figs.6 and 7 as shown above);
forming a second ILD layer (114 top portion) over the gate structures (158) (see Zhou, Figs.6 and 7 as shown above);
forming openings in the second ILD layer (114 top potion) (see Zhou, Figs.6 and 7 as shown above); and
forming conductive layers (112) in the openings to form source and drain structures (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 24: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 7 as above. The combination of Zhou and Lee further teaches wherein forming an insulating layer (note: a portion of insulating layer 114 which is formed between the back side of the main substrate and the first back side power supply wiring is equivalent to the claimed limitation of “insulating layer”) on the back side of the main substrate (100) (see Zhou, Fig. 7 as shown above).
Regarding Claim 25: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 24 as above. The combination of Zhou and Lee further teaches wherein the TSVs (200) pass through the insulating layer (note: a portion of insulating layer 114 which is formed between the back side of the main substrate and the first back side power supply wiring is equivalent to the claimed limitation of “insulating layer”) (see Zhou, Fig. 7 as shown above).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. 2019/0273119 A1, hereinafter refer to Zhou) and Lee et al. (U.S. 2015/0364425 A1, hereinafter refer to Lee) as applied to claim 1 above, and further in view of Vellianitis (U.S. 2020/0105527 A1, hereinafter refer to Vellianitis).
Regarding Claim 9: Zhou as modified teaches a method of manufacturing a semiconductor device as applied to claim 1 above. The combination of Zhou and Lee further teaches wherein the thin film transistors (118) are formed by:
forming a semiconductor layer (150) over the first ILD layer (114 bottom portion) (see Zhou, Figs.6 and 7 as shown above);
forming gate structures (158) over the semiconductor layer (150) (see Zhou, Figs.6 and 7 as shown above);
forming a second ILD layer (114 top portion) over the gate structures (158) (see Zhou, Figs.6 and 7 as shown above);
forming an opening in the second ILD layer (114 top portion), in which the gate structures (158) are exposed (see Zhou, Figs.6 and 7 as shown above);
forming a conductive layer in the opening (see Zhou, Figs.6 and 7 as shown above).
The combination of Zhou and Lee is silent upon explicitly disclosing wherein performing a planarization operation on the conductive layer to form source and drain structures.
Before effective filing date of the claimed invention the disclosed processing conditions were known in order to remove excess conductive material from the ILD layer.
For support see Vellianitis, which teaches wherein performing a planarization operation on the conductive layer to form source and drain structures (85) (see Vellianitis, Fig.13 and ¶ [0062]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou, Lee, and Vellianitis to enable performing a planarization operation on the conductive layer of Zhou to form source and drain structures as taught by Vellianitis in order to remove excess conductive material from the ILD layer.
Claim(s) 10-13, 16, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. 2019/0273119 A1, hereinafter refer to Zhou) in view of Lee et al. (U.S. 2015/0364425 A1, hereinafter refer to Lee), Cho et al. (U.S. 2017/0125364 A1, hereinafter refer to Cho), and Takeno et al. (U.S. 2018/0315743 A1, hereinafter refer to Takeno).
Regarding Claim 10: Zhou discloses a method of manufacturing a semiconductor device (see Zhou, Figs.6 and 7 as shown above and ¶ [0001]), comprising:
forming a front side circuit (102) at a front side of a main substrate (100), the front side circuit (102) including fin field effect transistors (FinFETs) ((note: a front side circuit 102 is a non-planar transistor which is the fin is formed between isolation insulating layer and known to be considered as a fin field effect transistors (FinFETs)) with fin structures extending in a first direction, and buried conductive lines (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive lines”) disposed between the fin structures (note: the protruding region of the substrate 100 is equivalent to the claimed limitation of “fin structures of the FinFETs”) (see Zhou, Fig.7 as shown above);
forming through-silicon-vias (TSVs) (200) passing through the main substrate (100) to be connected to the front side circuit (102) (see Zhou, Figs.6 and 7 as shown above);
forming back side power supply wirings including a pair of first main power supply wirings for supplying a first voltage, and a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view (cross-sectional view), the back side power supply wirings extending in the first direction (see Zhou, Figs.6 and 7 as shown above);
forming a first interlayer dielectric (ILD) layer (114 bottom portion) over the back side power supply wirings (see Zhou, Figs.6 and 7 as shown above); and
forming thin film transistors (118) over the first ILD layer (114 bottom portion) to be coupled to the pair of first main power supply wirings and the first local power supply wiring (see Zhou, Figs.6 and 7 as shown above and Figs.2-3),
wherein the first local power supply wiring is coupled to the front side circuit (102) via one or more of the TSVs (200) (see Zhou, Figs.6 and 7 as shown above).
Zhou is silent upon explicitly disclosing wherein attaching a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit.
For support see Lee, which teaches wherein attaching a sacrificial substrate (200) with a bonding layer (208) to a the front side of the main substrate (100) over the front side circuit (see Lee, Figs.1-3, 14, and 20 as shown above and ¶ [0024]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou and Lee to enable to attach a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit of Zhou as taught by Lee in order to protect the front side circuit from damage during subsequent processing steps.
The combination of Zhou and Lee is silent upon explicitly disclosing wherein the TSVs are arranged in a matrix having a first pitch along the first direction and a second pitch along a second direction crossing the first direction, and
the first pitch is in a range from 120 nm to 480 nm.
For support see Cho, which teaches wherein the TSVs are arranged in a matrix having a first pitch along the first direction and a second pitch along a second direction crossing the first direction (see Cho, Figs.2A-2B as shown below, ¶ [0021], ¶ [0035], and ¶ [0121]), and
the first pitch (P1) is in a range from 120 nm to 480 nm (equal to or less than about 150 μm) (see Cho, Figs.2A-2B as shown below, ¶ [0021], ¶ [0035], and ¶ [0121]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou, Lee, and Cho to enable The Zhou TSVs to be arranged according to the teachings of Cho in order to simplify manufacturing process of an integrated circuit device including a TSV device and improve the productivity.
The combination of Zhou, Lee, and Cho teaches a larger pitch ranges than the claimed invention; however, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the pitch ranges between TSVs through routine experimentation and optimization to obtain optimal or desired device performance because the pitch ranges between TSVs is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
The combination of Zhou, Lee, and Cho is silent upon explicitly disclosing wherein a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view.
For support see Takeno, which teaches wherein a first local power supply wiring (206) for supplying the first voltage disposed between the pair of first main power supply wirings (205A/205B) in plan view (see Takeno, Fig.17 as shown below).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou, Lee, Cho, and Takeno to enable the back side power supply wirings of Kim to include a pair of first main power supply wirings for supplying a first voltage, and a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view as taught by Takeno in order to supply power for semiconductor device.
Regarding Claim 11: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 10 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein the back side power supply wirings further include a pair of second main power supply wirings for supplying a second voltage different from the first voltage (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 12: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 11 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein the pair of first main power supply wirings and the first local power supply wiring are disposed between the pair of second main power supply wirings in plan view (see Takeno, Fig.17 as shown above).
Regarding Claim 13: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 12 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein the pair of second main power supply wirings are coupled to the front side circuit (102) via one or more of the TSVs (200) (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 16: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 10 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein the first pitch is equal to the second pitch (see Cho, Figs.2A-2B as shown above).
Regarding Claim 21: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 10 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein forming a second ILD layer (114 top portion) over the thin film transistors (118) (see Zhou, Figs.6 and 7 as shown above); and
forming electrodes connected to thin film transistors (118) (see Zhou, Figs.6 and 7 as shown above).
Regarding Claim 22: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 10 as above. The combination of Zhou, Lee, Cho, and Takeno further teaches wherein the thin film transistors (118) are formed by:
forming a semiconductor layer (150) over the first ILD layer (114 bottom portion) (see Zhou, Figs.6 and 7 as shown above);
forming gate structures (158) over the semiconductor layer (150) (see Zhou, Figs.6 and 7 as shown above);
forming a second ILD layer (114 top portion) over the gate structures (158);
forming openings in the second ILD layer (114 top portion) (see Zhou, Figs.6 and 7 as shown above); and
forming conductive layers in the openings to form source and drain structures (see Zhou, Figs.6 and 7 as shown above).
Claim(s) 17- 18 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. 2019/0273119 A1, hereinafter refer to Zhou) in view of Lee et al. (U.S. 2015/0364425 A1, hereinafter refer to Lee) and Takeno et al. (U.S. 2018/0315743 A1, hereinafter refer to Takeno).
Regarding Claim 17: Zhou discloses a method of manufacturing a semiconductor device (see Zhou, Figs.6 and 7 as shown above and ¶ [0001]), comprising:
forming a front side circuit (102) at a front side of a main substrate (100), the front side circuit (102) including fin field effect transistors (FinFETs) ((note: a front side circuit 102 is a non-planar transistor which is the fin is formed between isolation insulating layer and known to be considered as a fin field effect transistors (FinFETs)) with fin structures extending in a first direction and buried conductive lines (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive lines”) disposed between the fin structures (see Zhou, Fig.7 as shown above);
forming through-silicon-vias (TSVs) (200) passing through the main substrate (100) to be connected to the buried conductive lines (note: a portion of TSV 200 which is buried within the substrate 100 and isolation insulating layer is equivalent to the claimed limitation of “buried conductive lines”) (see Zhou, Fig. 7 as shown above);
forming back side power supply wirings including a pair of first main power supply wirings for supplying a first voltage, and a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view (in cross-sectional view), the back side power supply wirings extending in the first direction (see Zhou, Figs.6 and 7 as shown above);
forming a first interlayer dielectric (ILD) layer (114 bottom portion) over the back side power supply wirings (see Zhou, Figs.6 and 7 as shown above); and
forming thin film transistors (118) over the first ILD layer (114 bottom portion) to be coupled to the pair of first main power supply wirings and the first local power supply wiring (see Zhou, Figs.6 and 7 as shown above and Figs.2-3),
wherein the first local power supply wiring is coupled to the front side circuit (102) via one or more of the TSVs (200) (see Zhou, Figs.6 and 7 as shown above and Figs.2-3), and
wherein the thin film transistors (118) are formed by:
forming a semiconductor layer (150) over the first ILD layer (114 bottom portion) (see Zhou, Figs.6 and 7 as shown above);
forming gate structures (158) over the semiconductor layer (150) (see Zhou, Figs.6 and 7 as shown above);
forming a second ILD layer (114 top portion) over the gate structures (158) (see Zhou, Figs.6 and 7 as shown above);
forming openings in the second ILD layer (114 top portion) (see Zhou, Figs.6 and 7 as shown above); and
forming conductive layers (112) in the openings to form source and drain structures (160/162) (see Zhou, Figs.6 and 7 as shown above).
Zhou is silent upon explicitly disclosing wherein attaching a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit.
For support see Lee, which teaches wherein attaching a sacrificial substrate (200) with a bonding layer (208) to a the front side of the main substrate (100) over the front side circuit (see Lee, Figs.1-3, 14, and 20 as shown above and ¶ [0024]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou and Lee to enable to attach a sacrificial substrate with a bonding layer to the front side of the main substrate over the front side circuit of Zhou as taught by Lee in order to protect the front side circuit from damage during subsequent processing steps.
The combination of Zhou and Lee is silent upon explicitly disclosing wherein a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view.
For support see Takeno, which teaches wherein a first local power supply wiring (206) for supplying the first voltage disposed between the pair of first main power supply wirings (205A/205B) in plan view (see Takeno, Fig.17 as shown above).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou, Lee, and Takeno to enable the back side power supply wirings of Kim to include a pair of first main power supply wirings for supplying a first voltage, and a first local power supply wiring for supplying the first voltage disposed between the pair of first main power supply wirings in plan view as taught by Takeno in order to supply power for semiconductor device.
Regarding Claim 18: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 17 as above. The combination of Zhou, Lee, and Takeno further teaches wherein the buried conductive lines (a portion of TSV 200) are formed by: after forming the fin structures, forming an isolation insulating layer (see Zhou, Fig.7 as shown above);
forming trenches between the fin structures (see Zhou, Fig.7 as shown above); and
forming the buried conductive lines (a portion of TSV 200) in the trenches (see Zhou, Fig.7 as shown above).
Regarding Claim 23: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 18 as above. The combination of Zhou, Lee, and Takeno further teaches forming a second ILD layer (114 top potion) over the thin film transistors (118) (see Zhou, Figs.6 and 7 as shown above); and
forming electrodes connected to thin film transistors (118) (see Zhou, Figs.6 and 7 as shown above).
Claim(s) 19- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (U.S. 2019/0273119 A1, hereinafter refer to Zhou), Lee et al. (U.S. 2015/0364425 A1, hereinafter refer to Lee), and Takeno et al. (U.S. 2018/0315743 A1, hereinafter refer to Takeno) as applied to claim 18 above, and further in view of Kim et al. (U.S. 2021/0028112 A1, hereinafter refer to Kim).
Regarding Claims 19 and 20: Zhou as modified teaches a method of manufacturing a semiconductor device as set forth in claim 18 as above. The combination of Zhou, Lee, and Takeno is silent upon explicitly disclosing wherein the conductive lines are formed by:
filling the trenches with a conductive material;
recessing the filled conductive material; and
forming insulating layers over the recessed conductive material (as claimed in claim 19);
wherein before the conductive lines are formed, a liner insulating layer is formed on sides and a bottom of the trenches (as claimed in claim 20).
For support see Kim, which teaches wherein the conductive lines (120) are formed by: filling the trenches (H) with a conductive material (122/125) (see Kim, Figs.10A- 10E);
recessing the filled conductive material (122/125) (see Kim, Figs.10A- 10E); and
forming insulating layers (130) over the recessed conductive material (122/125) (see Kim, Figs.10A- 10E) (as claimed in claim 19);
wherein before the conductive lines (120) are formed, a liner insulating layer (122) is formed on sides and a bottom of the trenches (H) (see Kim, Figs.10A- 10E) (as claimed in claim 20).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhou, Lee, Takeno, and Kim to enable the known processing conditions as taught by Kim in order to form buried interconnect layer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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