DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/06/2026 has been entered.
Response to Amendment
Claims 1, 6, 12, 19 and 20 have been amended; and claims 1-20 are currently pending.
Claim Objections
Claim 15 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 12. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 14, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2009/0053899 A1, hereinafter “Liu”) in view of Torii (US 20110101462 A1, hereinafter “Torii”) and Liaw (US 2011/0069527 A1 hereinafter “Liaw”).
In regards to claim 12, Liu discloses (See, for example, annotated Fig. 1 included below) a semiconductor device, comprising:
a plurality of active regions (110) parallel with one another, the plurality of active regions (100) extending along a first lateral direction (1st); and
a plurality of gate structures (120) parallel with one another, the plurality of gate structures (120) extending along a second lateral direction (2nd) perpendicular to the first lateral direction (1st), wherein each of the plurality of gate structures (120) comprises one or more discrete segments physically separated by respective gaps (See, for example, GAP1 and GAP2);
wherein at least a first one of the plurality of gate structures (1001) comprises a first segment (1001A) overlaying a first number of the plurality of active regions (ACT1), and at least a second one of the plurality of gate structures (1002”), disposed adjacent the first gate structure (1001), comprises a second segment (1002B) overlaying a second number of the plurality of active regions (ACT2);
wherein the first segment (1001A) is shifted away from the second segment (1002B) along the second lateral direction (2nd).
Liu is silent about
each of the plurality of active regions and a corresponding subset of the plurality of gate structures operatively form a plurality of transistors; and wherein a first subset of the plurality of
transistors have a first threshold voltage, and a second subset of the plurality of transistors have a second threshold voltage different from the first threshold voltage.
Torii discloses (See, for example, Figs. 1-3) each of the plurality of active regions (12a-12h) and a corresponding subset of the plurality of gate structures (20a, 20b) operatively form a
plurality of transistors (34, 36); and wherein a first subset of the plurality of transistors (See, for example, 34) have a first threshold voltage, and a second subset of the plurality of transistors
(see, for example, 36) have a second threshold voltage different from the first threshold voltage (PMPOS and NMOS ).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Torii because this would help improve carrier mobility so that the ON-current of the transistor is improved.
Liu as modified above further fails to explicitly teach that wherein an intersection of the at least one of the plurality of active regions and a corresponding one of the plurality of gate structures form a Read-Only-Memory (ROM) cell.
Liaw while disclosing a ROM cell teaches (See, for example, Fig. 2) an intersection of the at least one of the plurality of active regions (116) and a corresponding one of the plurality of
gate structures (word line gate 104) form a Read-Only-Memory (ROM) cell (See, for example, Par [0021]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Liaw because Liaw explicitly recognizes that managing the layout-dependent effects on gate structures in ROM arrays including the poly
spacing effect (PSE), STI stress effects, and OD extension-induced threshold voltage variations is critical for achieving device matching and reliable ROM operation
In regards to claim 19, Liu discloses (See, for example, annotated Fig. 1 included below) a
method for fabricating memory devices, comprising: forming a plurality of active regions (110) parallel with one another, wherein the plurality of active regions (110) extend along a first lateral direction (1st); forming a plurality of gate structures (120) parallel with one another,
wherein the plurality of gate structures (120) extend along a second lateral direction (2nd)
perpendicular to the first lateral direction (1st), wherein each of the plurality of gate structures
(120) overlays the plurality of active regions (110); and
separating (via, for example, GAP1 and GAP2) each of the plurality of gate structures into a respective set of discrete segments (for example, 1001A, 1002B…);
wherein at least a first one of the plurality of gate structures (1001) comprises a first segment (1001A), and at least a second one of the plurality of gate structures (1002”), disposed adjacent the first gate structure (1001), comprises a second segment (1002B);
wherein the first segment (1001A) is shifted away from the second segment (1002B) along the second lateral direction (2nd).
Liu is silent about the first segment and the second segment have the same length.
Torii discloses (See, for example, Figs. 1-3) the first segment (20a, on 12a) and the second segment (20a, on 12c) have the same length (same channel length, See, for example, Fig. 3).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Torii because this would help improve carrier mobility so that the ON-current of the transistor is improved.
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Liu as modified above further fails to explicitly teach that wherein an intersection of the at least one of the plurality of active regions and a corresponding one of the plurality of gate structures operatively form a Read-Only-Memory (ROM) cell.
Liaw while disclosing a ROM cell teaches (See, for example, Fig. 2) an intersection of the at least one of the plurality of active regions (116) and a corresponding one of the plurality of gate structures (word line gate 104) operatively form a Read-Only-Memory (ROM) cell (See, for example, Par [0021]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Liu by Liaw because Liaw explicitly recognizes that managing the layout-dependent effects on gate structures in ROM arrays including the poly spacing effect (PSE), STI stress effects, and OD extension-induced threshold voltage variations is critical for achieving device matching and reliable ROM operation
In regards to claim 14, Liu discloses (See, for example, annotated Fig. 1 included above) the first number (assuming the first number of the plurality of active regions overlayed by the first segment) is different from the second number (assuming the second number of the plurality of active regions overlayed by the second segment).
In regards to claim 16, Liu discloses (See, for example, annotated Fig. 1 included above) the first segment (1001A) is shifted away from the second segment (1002B) along the second lateral direction (2nd) with a third number of the plurality of active regions.
In regards to claim 17, Liu discloses (See, for example, annotated Fig. 1 included above) the first number, second number, and third number are each an integer equal to or greater than 1. (assuming the first, the second, and the third number of the plurality of active regions overlayed by the respective segments).
In regards to claim 18, Liu as modified by Torii discloses (See, for example, Figs. 22) the plurality of transistors form a Read Only Memory (ROM) array (See, for example, Pars
[0090]-[0092], [0102]); wherein a number of the first subset of transistors (See, for example, transistors in active regions 12a, 12b, 12e and 12f) is equal to a number of the second subset of transistors (See, for example, transistors in active regions 12c, 12d, 12g and 12h).
Allowable Subject Matter
Claim 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-11 are allowed over the prior arts of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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