DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/10/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-12 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (PG Pub 2012/0193785; hereinafter Lin).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches a structure, comprising:
a substrate (annotated “sub” in Fig. 3 above) comprising a front-side surface (top) and a back-side surface (bottom);
a first through-via 40 (“via-1”) disposed in the substrate (see Fig. 3);
a first interconnect structure (annotated “RDL-1” in Fig. 3 above) disposed on the back-side surface of the substrate and electrically connected to the first through-via (see Fig. 3);
a via rail 86 (“rail”) disposed on the front-side surface of the substrate (see Fig. 3); and
a second interconnect structure (annotated “RDL-2” in Fig. 3 above), comprising:
a dielectric layer (accumulation of layers built up to form RDL-2) disposed on the via rail (see Fig. 3);
a plurality of interconnect levels (all metal layers within the dielectric layers) disposed in the dielectric layer (see Fig. 3); and
a second through-via (annotated “via-2” in Fig. 3 above) extending from a bottommost interconnect level in the plurality of interconnect levels to a topmost interconnect level in the plurality of interconnect levels (see Fig. 3).
Regarding claim 2, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the first through-via (“via-1”) extends from the front-side surface to the back-side surface of the substrate (from the top to the bottom of the sub) (see Fig. 3).
Regarding claim 3, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the second through-via (“via-2”) s electrically connected to a metal line 26 of the bottommost interconnect level 28 and to a metal line of the topmost interconnect level (86 of RDL-2).
Regarding claim 4, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the second through-via (“via-2”) is electrically connected to the via rail 86 (see Fig. 3).
Regarding claim 5, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the first through-via (“via-1”) is aligned to the second through-via (“via-2” (see Fig. 3).
Regarding claim 9, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the first interconnect structure (“RDL-1”) comprises a via structure (annotated “via structure” in Fig. 3 above) electrically connected to the first (“via-1”) and second through-vias (“via-2”) (see Fig. 3).
Regarding claim 10, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin the first interconnect structure (“RDL-1”) comprises a via structure vertically stacked with the first (“via-1”) and second through-vias (“via-2”) (see Fig. 3).
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Regarding claim 11, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches a structure, comprising:
a substrate (annotated “sub” in Fig. 3 above) comprising a first surface (top) and a second surface (bottom);
a through-silicon via (“via-1”) extending from the first surface to the second surface of the substrate (see Fig. 3);
a first interconnect structure (annotated “RDL-1” in Fig. 3 above) disposed on the first surface of the substrate (see Fig. 3);
a via rail 86 (“rail”) disposed on the second surface of the substrate (see Fig. 3);
a device layer (annotated “device” in Fig. 3 above), disposed on the via rail (indirectly), comprising a semiconductor device 7 and a via structure (annotated “via struct” in Fig. 3 above); and
a second interconnect structure (annotated “RDL-2” in Fig. 3 above), comprising: a dielectric layer (annotated “dielectric” in Fig. 3 above) disposed on the device layer (see Fig. 3);
a stack of interconnect layers (all metal layers within the dielectric layers) disposed in the dielectric layer (see Fig. 3);
a first through-via (annotated “thru via-1” in Fig. 3 above) extending from a bottommost interconnect layer in the stack of interconnect layers to a mid-level interconnect layer in the stack of interconnect layers (see Fig. 3); and
a second through-via (annotated “thru via-2” in Fig. 3 above) extending from the mid-level interconnect layer to a topmost interconnect layer in the stack of interconnect layers (see Fig. 3).
Regarding claim 12, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the second through-via (thru-via-2”) is vertically stacked on the first through-via (thru-via-1”) (see Fig. 3).
Regarding claim 15, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the stack of interconnect layers (all metal layers within the dielectric layers) including the bottommost interconnect layer and the mid-level interconnect layer (see Fig. 3), he does not explicitly teach “a plurality of interconnect layers between the bottommost interconnect layer and the mid-level interconnect layer.”
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of interconnect layers between the bottommost interconnect layer and the mid-level interconnect layer, since it has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)). It is the Examiner’s position that no new and unexpected result is produced, therefore the modification of duplicating parts is not a patentable feature for the invention as claimed. As a result, requiring a rationale for modifying a reference is moot because the modification is, under Harza, not a patentable feature.
Regarding claim 16, refer to the Examiner’s mark-up of Fig. 3 provided above, Lin teaches the stack of interconnect layers (all metal layers within the dielectric layers) including the bottommost interconnect layer and the mid-level interconnect layer (see Fig. 3), he does not explicitly teach “a plurality of interconnect layers between the mid-level interconnect layer and the topmost interconnect layer.”
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the number of interconnect layers between the mid-level interconnect layer and the topmost interconnect layer, since it has been held that the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)). It is the Examiner’s position that no new and unexpected result is produced, therefore the modification of duplicating parts is not a patentable feature for the invention as claimed. As a result, requiring a rationale for modifying a reference is moot because the modification is, under Harza, not a patentable feature.
Prior Art
2. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a. Liu (PG Pub 2017/0125383) teaches a hybrid three-dimensional integrated circuit reconfigurable thermal aware and dynamic power gating interconnect architecture.
b. Yang (PG Pub 2015/0091130) teaches a vertical noise reduction in 3d stacked semiconductor devices.
Allowable Subject Matter
3. Claims 17-20 are allowable.
Claims 6-8 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 6, a device layer disposed between the second interconnect structure and the via rail. Claims 7-8 would be allowable, because they depend on allowable claim 6.
Claim 17 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 17, a second microelectronic die package over the plurality of passive device contacts, the second package having a plurality of package contacts to connect to the plurality of passive device contacts. Claims 18-20 would be allowable, because they depend on allowable claim 17.
Claim 13 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 13, the second interconnect structure further comprises: a third through-via extending from the bottommost interconnect layer to the mid-level interconnect layer; and a via tower comprising a stack of vias extending from the mid-level interconnect layer to the topmost interconnect layer.
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, the through-silicon via, the via structure, the first through- via, and the second through-via are vertically stacked on each other.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817