DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-10, 17-26 pending.
Claims 21-26 new
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10, 17-26 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (U.S. 2016/0334362), Nakamura (U.S. 2006/0096972) and further in view of Kuemin et al (U.S. 2016/0011134).
Regarding claim 1. Liu et al discloses a method (FIG. 1-21), comprising: depositing a dielectric layer (FIG. 1A, item 131) on a first surface of a semiconductor layer (FIG. 1A, item 155);
forming a primary gate stack (FIG. 1A, item 131, 133) in the dielectric layer (FIG. 1A, item 131) and on the first surface of the semiconductor layer (FIG. 1A, item 155);
forming a secondary gate stack (FIG. 1A, item 119, 121) on a second surface of the semiconductor layer (FIG. 1A, item 155); and
forming a heater (FIG. 1A, item 113A), in the dielectric layer (FIG. 1A, item 131, 154),
comprising: forming ring-shaped heating elements in a concentric arrangement ([0050], i.e. heating elements 113 surrounds on four sides);
Liu et al fails to explicitly disclose
wherein each of the ring-shaped heating elements comprises a closed circular cross sectional profile;
electrically connecting a first connection point of an innermost heating element to a first connection point of an outermost heating element from the ring-shaped heating elements; electrically connecting a second connection point of the innermost heating element to a first voltage source; and electrically connecting a second connection point of the outermost heating element to a second voltage source different from the first voltage source.
However, Nakamura teaches wherein each of the ring-shaped heating elements comprises a closed circular cross sectional profile (FIG. 3A; [0146], i.e. the mount surface is divided into resistive heating member zone 4a of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones 4b, 4cd, 4eh located concentrically on the outside thereof);
Since Liu et al and Nakamura teach heating elements, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al with the teachings of wherein each of the ring-shaped heating elements comprises a closed circular cross sectional profile as disclosed by Nakamura. The use of heating member zone of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones located concentrically on the outside thereof in Nakamura provides for improving the performance of uniformly heating the wafer (Nakamura, [0146]).
Liu et al and Nakamura fails to explicitly disclose
electrically connecting a first connection point of an innermost heating element to a first connection point of an outermost heating element from the ring-shaped heating elements; electrically connecting a second connection point of the innermost heating element to a first voltage source; and electrically connecting a second connection point of the outermost heating element to a second voltage source different from the first voltage source.
However, Kuemin et al teaches electrically connecting ([0055]-[0056]) a first connection point (FIG. 3, item 20b) of an innermost heating element (FIG. 3, item 21b) to a first connection point (FIG. 3, item 20b) of an outermost heating element (FIG. 3, item 21e) from the ring-shaped heating elements (FIG. 3; [Abstract], i.e. Each heater element comprises an inner section, an intermediate section and an outer section arranged in series); electrically connecting ([0055]-[0056]) a second connection point (FIG. 3, item 20a) of the innermost heating element (FIG. 3, item 21b) to a first voltage source (FIG. 3, item 9b; [0048]); and electrically connecting ([0055]-[0056]) a second connection point (FIG. 3, item 9a) of the outermost heating element (FIG. 3, item 21e) to a second voltage source (FIG. 3, item 9a; [0048]) different from the first voltage source (FIG. 3, item 9b; [0048]).
Since Liu et al, Nakamura and Kuemin et al teach heating elements, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al and Nakamura with the teachings of the electrically connecting a first connection point of an innermost heating element to a first connection point of an outermost heating element from the ring-shaped heating elements; electrically connecting a second connection point of the innermost heating element to a first voltage source; and electrically connecting a second connection point of the outermost heating element to a second voltage source different from the first voltage source as disclosed by Kuemin et al. The use of the heater element comprises an inner section, an intermediate section and an outer section arranged in series in Kuemin et al provides for generating more heat in the periphery of the hotplate for a uniform temperature distribution (Kuemin et al, [0015]).
Regarding claim 2. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Liu et al further discloses wherein forming the primary gate stack (FIG. 1A, item 131, 133) comprises: depositing a gate dielectric (FIG. 1A, item 131) on the first surface of the semiconductor layer (FIG. 1A, item 155); and depositing a gate electrode (FIG. 1A, item 133) on the gate dielectric (FIG. 1A, item 131).
Regarding claim 3. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Liu et al further discloses wherein forming the secondary gate stack (FIG. 1A, item 121, 119) comprises: depositing a gate dielectric (FIG. 1A, item 121) on the second surface of the semiconductor layer (FIG. 1A, item 155); and
depositing a capture reagent (FIG. 1A, item 119) on the gate dielectric (FIG. 1A, item 121).
Regarding claim 4. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1,
Kuemin et al further discloses wherein the first connection points (FIG. 3a, item 20b) are at a first end (FIG. 3a, item 20b) of a quadrant (FIG. 3a, item 20a and 20b) of the ring-shaped heating elements (FIG. 3a, item 6a) and the second connection points (FIG. 3a, item 20a) are at a second end (FIG. 3a, item 20a) of the quadrant (FIG. 3a, item 20a and 20b) of the ring-shaped heating elements (FIG. 3a, item 6a).
Regarding claim 5. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Liu et al further discloses further comprising forming a temperature sensor (FIG. 11, item 111A) in the semiconductor layer (FIG. 11, item 155).
Regarding claim 6. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Liu et al further discloses further comprising forming a temperature sensor (FIG. 11, item 111A) in the semiconductor layer (FIG. 11, item 155) prior to forming (FIG. 4, item 271) the secondary gate stack (FIG. 21, item 121).
Regarding claim 7. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Kuemin et al further discloses wherein forming the heater further comprises electrically connecting ([0055]-[0056]) a third connection point (FIG. 3, item 20a) of the innermost heating element (FIG. 3, item 21b) to a third connection point (FIG. 3, item 20a) of the outermost heating element (FIG. 3a, item 21e); and wherein the first (FIG. 3, item 20b) and third connection points (FIG. 3, item 20a) are in opposite quadrants (FIG. 3a, item 20a and 20b) of the ring-shaped heating elements (FIG. 3a, item 6a).
Regarding claim 8. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Kuemin et al further discloses wherein forming the heater further comprises: electrically connecting ([0055]-[0056]) a fourth connection point (FIG. 3, item 20b) of the innermost heating element (FIG. 3, item 21b) to the first voltage source (FIG. 3, item 9b); electrically connecting ([0055]-[0056]) a fourth connection point (FIG. 3, item 20b) of the outermost heating element (FIG. 3a, item 21b) to the second voltage source (FIG. 3, item 9a); and wherein the second (FIG. 3, item 20a) and fourth connection (FIG. 3, item 20b) points are in opposite quadrants (FIG. 3a, item 20a and 20b) of the ring- shaped heating elements (FIG. 3a, item 6a).
Regarding claim 9. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Kuemin et al further discloses wherein electrically connecting ([0055]-[0056]) the second connection point (FIG. 3, item 20a) of the innermost heating element (FIG. 3, item 21b) to the first voltage source (FIG. 3, item 9b) comprises electrically connecting ([0055]-[0056]) the second connection point (FIG. 3, item 20a) of the innermost heating element (FIG. 3, item 21b) to a ground voltage ([0014], i.e. for a given current flowing through the heater element, the current density in the outer section is larger than in the inner section; [0015], i.e. this design is well suited for low-voltage applications.).
Regarding claim 10. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 1.
Kuemin et al further discloses wherein electrically connecting ([0055]-[0056]) the second connection point (FIG. 3, item 20b) of the outermost heating element (FIG. 3, item 21e) to the second voltage source (FIG. 3, item 9a) comprises electrically connecting ([0055]-[0056]) the second connection point (FIG. 3, item 20b) of the outermost heating element (FIG. 3, item 21e) to a supply voltage source (FIG. 3, item 9a; [0048]).
Regarding claim 17. Liu et al disclose a method (FIG. 1-21), comprising:
forming a dual gate field effect transistor (FET) (FIG. 1A, item 126) on a substrate (FIG. 1A, item 155); depositing a dielectric layer (FIG. 1A, item 153 and 154) on the dual gate FET (FIG. 1A, item 126);
forming a multi-level interconnect structure (FIG. 1A, item 144) in the dielectric layer (FIG. 1A, item 153); and
forming a heater (FIG. 1A, item 113A) electrically connected ([0022]) to the multi-level interconnect structure (FIG. 1A, item 144),
wherein forming the heater comprises: forming a plurality of ring-shaped heating elements ([0050]) in a concentric arrangement ([0050], i.e. heating elements 113 surrounds on four sides).
Liu et al fails to explicitly disclose
wherein each of the ring-shaped heating elements in the plurality of ring-shaped heating elements comprises a closed circular cross-sectional profile;
electrically connecting a first connection point of an innermost heating element from the plurality of ring-shaped heating elements to a first connection point of an outermost heating element from the plurality of ring-shaped heating elements; and
electrically connecting a second connection point of a first heating element from the plurality of ring-shaped heating elements to a second connection point of a second heating element from the plurality of ring-shaped heating elements, wherein the first heating element is adjacent to the innermost heating element and the second heating element is adjacent to the outermost heating element
electrically connecting an innermost heating element from the plurality of heating elements to a first voltage source; and electrically connecting an outermost heating element from the plurality of heating elements to a second voltage source different from the first voltage source.
However, Nakamura teaches wherein each of the ring-shaped heating elements in the plurality of ring-shaped heating elements comprises a closed circular cross-sectional profile (FIG. 3A; [0146], i.e. the mount surface is divided into resistive heating member zone 4a of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones 4b, 4cd, 4eh located concentrically on the outside thereof);
Since Liu et al and Nakamura teach heating elements, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al with the teachings of wherein each of the ring-shaped heating elements in the plurality of ring-shaped heating elements comprises a closed circular cross-sectional profile as disclosed by Nakamura. The use of heating member zone of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones located concentrically on the outside thereof in Nakamura provides for improving the performance of uniformly heating the wafer (Nakamura, [0146]).
Liu et al and Nakamura fails to explicitly disclose
electrically connecting a first connection point of an innermost heating element from the plurality of ring-shaped heating elements to a first connection point of an outermost heating element from the plurality of ring-shaped heating elements; and
electrically connecting a second connection point of a first heating element from the plurality of ring-shaped heating elements to a second connection point of a second heating element from the plurality of ring-shaped heating elements, wherein the first heating element is adjacent to the innermost heating element and the second heating element is adjacent to the outermost heating element
electrically connecting an innermost heating element from the plurality of heating elements to a first voltage source; and electrically connecting an outermost heating element from the plurality of heating elements to a second voltage source different from the first voltage source.
However, Kuemin et al teaches electrically connecting ([0055]-[0056]) a first connection point (FIG. 3, item 20b) of an innermost heating element (FIG. 3, item 21b) from the plurality of ring-shaped heating elements (FIG. 3; [Abstract]) to a first connection point (FIG. 3, item 20b) of an outermost heating element (FIG. 3, item 21e) from the plurality of ring-shaped heating elements (FIG. 3; [Abstract]); and
electrically connecting a second connection point (FIG. 3, item 20a) of a first heating element (FIG. 3, item 21c) from the plurality of ring-shaped heating elements (FIG. 3; [Abstract]) to a second connection point (FIG. 3, item 20a) of a second heating element (FIG. 3, item 21d) from the plurality of ring-shaped heating elements (FIG. 3; [Abstract]), wherein the first heating element (FIG. 3, item 21c) is adjacent to the innermost heating element (FIG. 3, item 21b) and the second heating element (FIG. 3, item 21d) is adjacent to the outermost heating element (FIG. 3, item 21e)
electrically connecting ([0055]-[0056]) an innermost heating element (FIG. 3, item 21b) from the plurality of heating elements (FIG. 3; [Abstract], i.e. Each heater element comprises an inner section, an intermediate section and an outer section arranged in series) to a first voltage source (FIG. 3, item 9a); and electrically connecting ([0055]-[0056]) an outermost heating element (FIG. 3, item 21e) from the plurality of heating elements (FIG. 3; [Abstract]) to a second voltage source (FIG. 3, item 9b) different from the first voltage source (FIG. 3, item 9a).
Since Both Liu et al and Kuemin et al teach heating elements, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al and Nakamura with the teachings of the electrically connecting a first connection point of an innermost heating element from the plurality of ring-shaped heating elements to a first connection point of an outermost heating element from the plurality of ring-shaped heating elements, and electrically connecting a second connection point of a first heating element from the plurality of ring-shaped heating elements to a second connection point of a second heating element from the plurality of ring-shaped heating elements, wherein the first heating element is adjacent to the innermost heating element and the second heating element is adjacent to the outermost heating element, electrically connecting an innermost heating element from the plurality of heating elements to a first voltage source; and electrically connecting an outermost heating element from the plurality of heating elements to a second voltage source different from the first voltage source as disclosed by Kuemin et al. The use of the heater element comprises an inner section, an intermediate section and an outer section arranged in series in Kuemin et al provides for generating more heat in the periphery of the hotplate for a uniform temperature distribution (Kuemin et al, [0015]).
Regarding claim 18. Liu et al, Nakamura, and Kuemin et al discloses all the limitations of the method of claim 17
Kuemin et all further discloses wherein electrically connecting ([0055]-[0056]) the innermost heating element (FIG. 3, item 21b) to the first voltage source (FIG. 3, item 9b) comprises electrically connecting ([0055]-[0056]) the innermost heating element (FIG. 3, item 21b) to a ground voltage ([0014], i.e. for a given current flowing through the heater element, the current density in the outer section is larger than in the inner section; [0015], i.e. this design is well suited for low-voltage applications.).
Regarding claim 19. Liu et al, Nakamura, and Kuemin et al discloses all the limitations of the method of claim 17
Kuemin et all further discloses wherein electrically connecting ([0055]-[0056]) the outermost heating (FIG. 3a, item 21e) element to the second voltage source (FIG. 3a, item 9a) comprises electrically connecting ([0055]-[0056]) the outermost heating element (FIG. 3a, item 21e) to a supply voltage source (FIG. 3a, item 9a; [0048]).
Regarding claim 20. Liu et al, Nakamura, and Kuemin et al discloses all the limitations of the method of claim 17
Liu et all further discloses wherein forming the dual gate FET comprises: depositing a first gate dielectric (FIG. 10, item 131) on a first surface of the substrate (FIG. 10, item 155);
depositing a gate electrode (FIG. 10, item 133) on the first gate dielectric (FIG. 10, item 131);
depositing a second gate dielectric (FIG. 20, item 121) on a second surface of the substrate (FIG. 10, item 155); and
depositing a capture reagent (FIG. 1A, item 119) on the second gate dielectric (FIG. 1A, item 127).
Regarding claim 21. Liu et al discloses a method (FIG. 1-21), comprising:
depositing a dielectric layer (FIG. 1A, item 153) on a first surface of a substrate (FIG. 1A, item 155);
forming a first gate (FIG. 1A, item 133) on the first surface (FIG. 1A, item 131) of the substrate (FIG. 1A, item 155); forming a second gate (FIG. 1A, item 119) on a second surface (FIG. 1A, item 121) of the substrate (FIG. 1A, item 155);
forming a multi-level interconnect structure (FIG. 1A, item 144) in the dielectric layer (FIG. 1A, item 153); and
forming a heater (FIG. 1A, item 113A) electrically connected ([0022]) to the multi-level interconnect structure (FIG. 1A, item 144),
Liu et al fails to explicitly disclose wherein forming the heater comprises:
forming first, second, third, and fourth ring-shaped heating elements in a concentric arrangement, wherein each of the first, second, third, and fourth heating elements comprises a closed circular cross-sectional profile;
electrically connecting a first connection point of the first ring-shaped heating element to a first connection point of the second ring-shaped heating element; and
electrically connecting a second connection point of the third ring-shaped heating element to a second connection point of the fourth ring-shaped heating element.
However, Nakamura teaches Liu et al fails to explicitly disclose wherein forming the heater comprises:
forming first, second, third, and fourth ring-shaped heating elements in a concentric arrangement, wherein each of the first, second, third, and fourth heating elements comprises a closed circular cross-sectional profile (FIG. 3A; [0146], i.e. the mount surface is divided into resistive heating member zone 4a of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones 4b, 4cd, 4eh located concentrically on the outside thereof);
Since Liu et al and Nakamura teach heating elements, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al with the teachings of forming first, second, third, and fourth ring-shaped heating elements in a concentric arrangement, wherein each of the first, second, third, and fourth heating elements comprises a closed circular cross-sectional profile as disclosed by Nakamura. The use of heating member zone of circular or ring shape located at the innermost position and three ring-shaped resistive heating member zones located concentrically on the outside thereof in Nakamura provides for improving the performance of uniformly heating the wafer (Nakamura, [0146]).
Liu et al and Nakamura fails to explicitly disclose
electrically connecting a first connection point of the first ring-shaped heating element to a first connection point of the second ring-shaped heating element; and
electrically connecting a second connection point of the third ring-shaped heating element to a second connection point of the fourth ring-shaped heating element.
However, Kuemin et al teaches electrically connecting ([0055]-[0056]) a first connection point (FIG. 3, item 20b) of the first ring-shaped heating element (FIG. 3, item 21b) to a first connection point (FIG. 3, item 20a) of the second ring-shaped heating element (FIG. 3, item 21e); and
electrically connecting ([0055]-[0056]) a second connection point (FIG. 3, item 20b) of the third ring-shaped heating element (FIG. 3, item 21c) to a second connection point (FIG. 3, item 20a) of the fourth ring-shaped heating element (FIG. 3, item 21e).
Since Liu et al, Nakamura, and Kuemin et al teach heating elements, It would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Liu et al and Nakamura with the teachings of the electrically connecting a first connection point of the first ring-shaped heating element to a first connection point of the second ring-shaped heating element, and electrically connecting a second connection point of the third ring-shaped heating element to a second connection point of the fourth ring-shaped heating element as disclosed by Kuemin et al. The use of the heater element comprises an inner section, an intermediate section and an outer section arranged in series in Kuemin et al provides for generating more heat in the periphery of the hotplate for a uniform temperature distribution (Kuemin et al, [0015]).
Regarding claim 22. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 21.
Kuemin et al further discloses wherein the first connection point (FIG. 3, item 20b) of the first ring-shaped heating element (FIG. 3, item 21b) is closer to the second connection point (FIG. 3, item 20b) of the third ring-shaped (FIG. 3, item 21c) than the first connection point (FIG. 3, item 20a) of the second ring-shaped heating element (FIG. 3, item 21e).
Regarding claim 23. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 21.
Kuemin et al further discloses wherein the third (FIG. 3, item 21c) and fourth (FIG. 3, item 21d) ring-shaped heating elements are disposed between the first (FIG. 3, item 21b) and second (FIG. 3, item 21e) ring-shaped heating elements.
Regarding claim 24. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 21.
Kuemin et al further discloses wherein the third (FIG. 3, item 21c) and fourth ring-shaped heating elements (FIG. 3, item 21d) are adjacent to each other (FIG. 3).
Regarding claim 25. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 21.
Kuemin et al further discloses where the first (FIG. 3, item 20b) and second (FIG. 3, item 20a) connection points are not physically connected to each other (FIG. 3 shows items 20b and 20a are separated from each other and therefore not physically connected to each other).
Regarding claim 26. Liu et al, Nakamura and Kuemin et al discloses all the limitations of the method of claim 21.
Kuemin et al further discloses wherein forming the second gate comprises: depositing a gate dielectric (FIG. 1A, item 121) on the second surface of the substrate (FIG. 1A, item 155); and depositing a capture reagent (FIG. 1A, item 119) on the gate dielectric (FIG. 1A, item 121).
Response to Arguments
Applicant's arguments filed August 18, 2025 have been fully considered but they are not persuasive.
On page 9 of applicant’s remarks, applicant appears to argue that Liu et al and Kuemin et al fails to disclose applicant’s amended claim limitations.
Examiner respectfully points out that Liu et al, Nakamura, and Kuemin et al discloses applicant’s claims.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Provancha et al (U.S. 6,242,722) discloses temperature controlled thin film circular heater.
Yoshida et al (U.S. 6,080,970) discloses wafer heating apparatus.
Carman et al (U.S. 5,294,778) discloses concentric electric heating elements.
Alepee et al (U.S. 2015/0212030) discloses a micro-hotplate device and sensor comprising such device.
Kalnitsky et al (U.S. 2017/0343498) embedded temperature control system for a biosensor.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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