Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to Election/Restrictions, applicant has amended the claims, therefore the restriction requirement has been withdrawn and claims 1-20 have been examined.
Claim Objection
Claims 11 and 18 are objected for claim language “prior forming the first cap layer on the first metal, forming a buffer dielectric layer on the first metal whereby the first metal is formed on the buffer dielectric layer” it’s not clear first metal is formed on the buffer layer or vice versa.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak et al. (US 2016/0133691, hereinafter Phatak) in view of Lai et al. (US 9,773,860, hereinafter Lai).
With respect to claim 1, Phatak discloses a method of manufacturing a metal-insulator-metal (MIM) device (Para 0008), the method comprising:
forming a first cap layer (Para 0035 – flash layer) on a first metal (102 of Fig. 1), wherein the first cap layer comprising a composition including at least zirconium and oxygen and having a tetragonal crystal phase (Para 0009; 0047; and 0050 – flash layer/bottom capping layer is formed on 102. This dielectric layer doped or undoped (ZrO2 based) is used to induce the tetragonal crystal phase of the adjacent dielectric – annealing creates tetragonal phase); forming an insulator layer (106) on the first cap layer (Para 0050 and 0055; bulk dielectric layer is disposed on the flash layer); forming a second cap layer disposed on the insulator layer (Para 0036 – capping layer), the second cap layer comprising a composition including at least zirconium and oxygen and having the having the tetragonal crystal phase (Para 0009; 0047 and 0050); forming a second metal disposed on the second cap layer (110 – Para 0060).
Phatak does not explicitly disclose that the insulator layer comprises of Hf1-xZrxO₂ .
In an analogous art, Lai discloses that the insulator layer comprises of Hf1-xZrxO₂ (Col. 2; lines 35-40 – hafnium zirconium oxide).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak’s method by having Lai’s disclosure in order to improve the insulating properties of a semiconductor device.
With respect to claim 5, Phatak discloses wherein the first cap layer
comprises ZrO₂ and the second cap layer comprises ZrO₂ (Para 0009; 0035; 0047; and 0050 – flash layer/bottom capping layer is formed on 102. This dielectric layer doped or undoped (ZrO2 based) is used to induce the tetragonal crystal phase of the adjacent dielectric).
With respect to claim 11, Phatak discloses prior forming the first cap layer on the first metal, forming a buffer dielectric layer on the first metal whereby the first metal is formed on the buffer dielectric layer (Para 0037 - there can be different layer above the first electrode and the flashing layer).
Claims 2 & 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak/Lai in view of Jin et al. (US 2022/0246716, hereinafter Jin).
With respect to claim 2, Phatak/Lai discloses the method of claim 1.
Pathak/Lai does not explicitly disclose wherein the tetragonal phase percentage of the first cap layer is at least 80%, and the tetragonal phase percentage of the second cap layer is at least 80%.
In an analogous art, Jin discloses wherein the tetragonal phase percentage of the first cap layer is at least 80%, and the tetragonal phase percentage of the second cap layer is at least 80% (Para 0051).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak/Lai’s method by having Jin’s disclosure in order to provide higher capacitance density in smaller area.
With respect to claim 6, Phatak/Lai discloses the method of claim 1.
Phatak/Lai does not explicitly disclose wherein the first cap layer
comprises a Hf1-xZrxO2 composition that is doped with a dopant, and second cap
layer comprises a Hf1-xZrxO₂ composition that is doped with the dopant, wherein
the dopant causes the tetragonal phase percentage of the first cap layer to be at
least 80% and the dopant causes the tetragonal phase percentage of the second
cap layer to be at least 80%.
In an analogous art, Jin discloses wherein the first cap layer comprises a Hf1-xZrxO2 composition that is doped with a dopant, and second cap layer comprises a Hf1-xZrxO₂ composition that is doped with the dopant (Para 0099 and 0101), wherein the dopant causes the tetragonal phase percentage of the first cap layer to be at least 80% and the dopant causes the tetragonal phase percentage of the second cap layer to be at least 80%.(Para 0051). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak/Lai’s method by having Jin’s disclosure in order to provide higher capacitance density in smaller area.
With respect to claim 7, Phatak/Lai does not explicitly disclose wherein the dopant comprises
silicon (Si), germanium (Ge), aluminum (AI), yttrium (Y), scandium (Sc), gadolinium (Gd), or a combination thereof.
In an analogous art, Jin discloses wherein the dopant comprises silicon (Si), germanium (Ge), aluminum (AI), yttrium (Y), scandium (Sc), gadolinium (Gd), or a combination thereof (Para 0099 ; silicon, germanium). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak/Lai’s method by having Jin’s disclosure in order to provide higher capacitance density in smaller area.
With respect to claim 8, Phatak/Lai does not explicitly disclose wherein the Hf1-xZrxO₂ insulator layer, the Hf1-xZrxO₂ composition of the first layer, and the Hf1-xZrxO₂ composition of the second layer all have the same zirconium fraction X.
In an analogous art, Jin discloses wherein the Hf1-xZrxO₂ insulator layer, the Hf1-xZrxO₂ composition of the first layer, and the Hf1-xZrxO₂ composition of the second layer all have the same zirconium fraction X (Para 0018; 0022; and 0057). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak’s method by having Lai’s disclosure in order to improve the insulating properties of a semiconductor device.
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak in view of Jin et al. (US 2022/0246716, hereinafter Jin).
With respect to claim 12, Phatak discloses a method of manufacturing a metal-insulator-metal (MIM) device (Para 0008), the method comprising:
forming a first cap layer (Para 0035 – flash layer) on a first metal (102 of Fig. 1), wherein the first cap layer comprises a dielectric material with a tetragonal phase (Para 0009; 0047; and 0050 – flash layer/bottom capping layer is formed on 102. This dielectric layer doped or undoped (ZrO2 based) is used to induce the tetragonal crystal phase of the adjacent dielectric – annealing creates tetragonal phase); forming an insulator layer (106) on the first cap layer (Para 0050 and 0055; bulk dielectric layer is disposed on the flash layer); forming a second cap layer on the insulator layer (Para 0036 – capping layer), wherein the second cap layer comprsing a dielectric material with a tetragonal crystal phase (Para 0009; 0047 and 0050); forming a second metal disposed on the second cap layer (110 – Para 0060).
Pathak does not explicitly disclose wherein the tetragonal phase percentage of the dielectric material of the first cap layer is at least 80%, and the tetragonal phase percentage of the dielectric material of the second cap layer is at least 80%.
In an analogous art, Jin discloses wherein the tetragonal phase percentage of the dielectric material of the first cap layer is at least 80%, and the tetragonal phase percentage of the dielectric material of the second cap layer is at least 80%. (Para 0051). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak’s method by having Jin’s disclosure in order to provide higher capacitance density in smaller area.
With respect to claim 18, Phatak discloses prior forming the first cap layer on the first metal, forming a buffer dielectric layer on the first metal whereby the first metal is formed on the buffer dielectric layer (Para 0037 - there can be different layer above the first electrode and the flashing layer).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Phatak/Jin in view of Liao et al. (US 2018/0331113, hereinafter Liao).
With respect to claim 13, Phatak/Jin discloses the method of claim 12.
Phatak/Jin does not explicitly disclose wherein the insulator layer
comprises a ferroelectric phase.
In an analogous art, Liao discloses wherein the insulator layer comprises a ferroelectric phase (Para 0016 and 0042). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak/Jin’s method by having Liao’s disclosure in order to improve the storage capabilities of a memory device.
With respect to claim 14, Phatak/Jin/Liao discloses the method of claim 13.
Phatak does not explicitly disclose wherein the insulator layer comprises an oxide selected from a group consisting of Hf1-xZrxO₂, SrBi₂Ta₂O₉, PbZrxTi1-xO3, or BaTiO3.
In an analogous art, Jin discloses wherein the insulator layer comprises an oxide selected from a group consisting of Hf1-xZrxO₂, SrBi₂Ta₂O₉, PbZrxTi1-xO3, or BaTiO3 (Para 0011-0012 - HfZrO). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak’s method by having Jin’s disclosure in order to provide higher capacitance density in smaller area.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Phatak.
With respect to claim 19, Phatak discloses a method of manufacturing a metal-insulator-metal (MIM) device (Para 0008), the method comprising:
forming a first metal (102 of Fig. 1 – Para 0053); forming a first cap layer disposed on the first metal (Para 0035 and 0037; flash layer), the first cap layer comprising a dielectric material having a tetragonal crystal phase (Para 0050 – flash layer/bottom capping layer is formed on 102. This dielectric layer doped or undoped (ZrO2 based) is used to induce the tetragonal crystal phase of the adjacent dielectric – annealing creates tetragonal phase); forming an insulator layer (106) disposed on the first cap layer (Para 0050 and 0055; bulk dielectric layer is disposed on the flash layer);
forming a second cap layer disposed on the insulator layer (Para 0036 – capping layer),
forming a second metal disposed on the second cap layer (110 – Para 0060).
In the same embodiment Phatak does not explicitly disclose that the first and the second cap layer comprising a dielectric material having a tetragonal crystal phase.
In another embodiment Phatak discloses the first cap and the second cap layer comprising a dielectric material having a tetragonal crystal phase (Para 0009; 0047; and 0050 – flash layer/bottom capping layer is formed on 102. This dielectric layer doped or undoped (ZrO2 based) is used to induce the tetragonal crystal phase of the adjacent dielectric – annealing creates tetragonal phase). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Phatak’s first embodiment by having the first and the second cap layer comprising a dielectric material having a tetragonal crystal phase to reduce the leakage current in semiconductor device.
Allowable Subject Matter
Claims 3-4, 9-10, 15-16, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 3, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the orthorhombic phase percentage of the Hf1-xZrxO₂ insulator layer is at least 70% causing the Hf1-xZrxO₂ insulator layer to be ferroelectric” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 4, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the first cap layer comprises a Hf1-xZrxO₂ composition that is more zirconium-rich than the Hf1-xZrxO₂ insulator layer, and the second cap layer comprises a Hf1-xZrxO₂ composition that is more zirconium-rich than the Hf1-xZrxO₂ insulator layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims
With respect to claim 9, none of the prior art on record disclose or render obvious the claimed limitations including “wherein a ratio of a thickness of the
first cap layer to the Hf1-xZrxO₂ insulator layer is 0.1 or less, and a ratio of a
thickness of the second cap layer to the Hf1-xZrxO2 insulator layer is 0.1 or less” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 15, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the insulator layer
comprises a ternary or quaternary oxide having a ferroelectric orthorhombic phase
whose phase percentage in the insulator layer is at least 70%, the first cap layer
comprises the ternary or quaternary oxide doped with a dopant, and second cap
layer comprises the ternary or quaternary oxide doped with the dopant, wherein the
dopant causes a tetragonal phase percentage of the first cap layer to be at least
80% and causes the tetragonal phase percentage of the second cap layer to be
at least 80%” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 16, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the insulator layer
comprises a ferroelectric Hf1-xZrxO₂ composition, and the first cap layer comprises
ZrO₂ or a Hf1-xZrxO₂ composition that is more zirconium-rich than the insulator
layer, and the second cap layer comprises ZrO₂ or a Hf1-xZrxO₂ composition that
is more zirconium-rich than the insulator layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 17, none of the prior art on record disclose or render obvious the claimed limitations including “wherein a ratio of a thickness of
the first cap layer to the insulator layer is 0.1 or less, and a ratio of a thickness of
the second cap layer to the insulator layer is 0.1 or less” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 20, none of the prior art on record disclose or render obvious the claimed limitations including “the insulator layer comprises a ferroelectric Hf1-xZrxO₂ material; and the first cap layer comprises ZrO₂ or a Hf1-xZrxO₂ composition that is more zirconium-rich than the insulator layer, and the second cap layer comprises ZrO₂ or a Hf1-xZrxO₂ composition that is more zirconium-rich than the insulator layer; and a ratio of a thickness of the first cap layer to the insulator layer is 0.1 or less, and a ratio of a thickness of the second cap layer to the insulator layer is 0.1
or less” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claim 10 has been objected because of it’s dependency on claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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