Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and 21-24 [the method] in the reply filed on12/23/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200027736 A1 Yoshida et al hereafter “Yoshida”, and further in view of US 20190378910 A1 Song et al hereafter “Song”, US 20170179284 A1 Kim et al hereafter “Kim [84]” and US 20170236821 A1 Kim et al hereafter “Kim [21]”.
Claim 1 Yoshida teaches a method, comprising:
forming a silicon structure (122 and 112 fig. 2A) on a substrate (116 fig. 2A);
depositing a first spacer layer (204 fig. 2A) on the polysilicon structure;
depositing a second spacer layer (206 fig. 2A) on the first spacer layer;
forming a source/drain (S/D) region (172 fig. 2I) on the substrate;
removing the second spacer layer [illustrated fig. 2E-2F, 206 is removed];
depositing a third spacer layer (205 fig. 2A,) on the first spacer layer and wherein the S/D region is formed below the third spacer layer [sufficiently illustrated fig. 2I];
depositing an interlayer dielectric (ILD) layer (168 fig. 2J) on the third spacer layer; and
replacing the silicon structure with a gate structure (276 fig. 2O)[illustrated fig. 2K-O].
Yoshida does not explicitly teach the silicon structure is “polysilicon”, depositing the third spacer layer on the S/D region, depositing an etch stop layer (ESL) on the third spacer layer; depositing the interlayer dielectric (ILD) layer on the etch stop layer.
Song teaches depositing a first spacer layer (220 fig. 14);
depositing a second spacer layer (230 fig. 14) on the first spacer layer;
forming a source/drain (S/D) region (240 fig. 16) on a substrate (200 fig. 17);
removing the second spacer layer [illustrated fig. 16-17];
depositing a third spacer layer (261 fig. 18) on the first spacer layer and on the S/D region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song such that “depositing the third spacer layer on the S/D region” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to “influencing the final electrical performance” and/or “achieving the effect of effectively reducing the parasitic capacitance between a contact hole and the gate” [Paragraph 0085-0086 Song]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods for forming a gate spacer.
Kim [84] teaches depositing an etch stop layer (comprising 160 and/or 150 fig. 5) on a spacer layer (125 and/or 125 fig. 5); depositing an interlayer dielectric (ILD) layer (191 fig. 5) on the etch stop layer .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song in further view of Kim [84] such that ‘depositing an etch stop layer (ESL) on the third spacer layer; depositing the interlayer dielectric (ILD) layer on the etch stop layer’ occurs.
A person of ordinary skill in the art would have been motivated to make this modification to “improving operation performance and reliability, by applying a stress liner to a source/drain region” [Paragraph 0006 Kim] and/or protecting the underlying layers from subsequent selective etch processes [sufficiently implied Paragraph 130 Kim].
Kim [21] teaches a gate replacement/dummy structure 115 [fig. 8] comprising polysilicon [Paragraph 0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song and Kim [84] in further view of Kim [21] such that the silicon structure is “polysilicon”.
A person of ordinary skill in the art would have been motivated to make this modification as selection of a known material for its known material properties is prima facie type obviousness [See MPEP 2144.07]. In this case it is the etch-selectivity of polysilicon and/or is function as a good dummy/replacement gate structure.
Claim 2 Yoshida in view of Song, Kim [84], and Kim [21] teach as shown above the method of claim 1, wherein depositing the first spacer layer comprises depositing a layer of dielectric material comprising a concentration of carbon atoms higher than a concentration of nitrogen atoms. [Yoshida discloses with sufficient specificity and embodiment of “SiO2” doped with “Carbon” for the first spacer layer within “a multilayer spacer structure of oxide/nitride/oxide layers 204/205/206 is formed over the other structures” and “Other formation techniques could also be used. It is also noted that nitride layers often include additional elements such as carbon (C), boron (B), oxygen (O), and/or other additives in addition to silicon nitride (SiN). Similarly, it is noted that oxide layers often include additional elements in addition to silicon dioxide (SiO.sub.2). Other variations could also be implemented” Paragraph 0032, this embodiment as matched contains no Nitrogen atoms thus the concentration of Carbon atoms is necessarily higher than that of Nitrogen atoms].
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song, Kim [84], and Kim [21] such that “wherein depositing the first spacer layer comprises depositing a layer of dielectric material comprising a concentration of carbon atoms higher than a concentration of nitrogen atoms” As a part of routine optimization result effected variables of the materials etch-selectivity and the dielectric constant [See MPEP 2144.05II]. In this case aligning the material properties of etch-selectivity and the dielectric constant closer to that of carbon than to that of Nitrogen.
Claims 3 Yoshida in view of Song, Kim [84], and Kim [21] the method of claim 1, wherein depositing the first spacer layer comprises depositing a layer comprising carbon [“carbon” disclosed with sufficient specificity paragraph 0032].
Yoshida in view of Song, Kim [84], and Kim [21] does not explicitly teach the layer is ‘carbon-rich’.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song, Kim [84], and Kim [21] such that the layer is ‘carbon-rich’ As a part of routine optimization result effected variables of the materials etch-selectivity and the dielectric constant [See MPEP 2144.05II]. In this case aligning the material properties of etch-selectivity and the dielectric constant closer to that of carbon.
Claim 8 Yoshida in view of Song, Kim [84], and Kim [21] teach as shown above the method of claim 1, wherein depositing the third spacer layer comprises depositing a layer of dielectric material comprising a concentration of nitrogen atoms [“Nitrogen” and/or “SiN” Yoshida paragraph 0032] and a concentration of carbon atoms [“carbon” Yoshida paragraph 0032].
Yoshida in view of Song, Kim [84], and Kim [21] does not teach the concentration of nitrogen atoms is higher than the concentration of carbon atoms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Song, Kim [84], and Kim [21] such that ‘the concentration of nitrogen atoms is higher than the concentration of carbon atoms’.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of the etch selectivity and/or dielectric constant of the third spacer layer and/or such that the etch selectivity and/or dielectric constant are closer to that of Nitrogen than that of Carbon [see MPEP 2144.05II].
Claim 9 Yoshida in view of Song, Kim [84], and Kim [21] teach as shown above the method of claim 1, wherein depositing the third spacer layer comprises depositing a layer of dielectric material comprising a concentration of nitrogen atoms higher than a concentration of nitrogen atoms in the first spacer layer [sufficiently disclosed Paragraph 0032 “a multilayer spacer structure of oxide/nitride/oxide layers 204/205/206” and “It is also noted that nitride layers often include additional elements such as carbon (C), boron (B), oxygen (O), and/or other additives in addition to silicon nitride (SiN). Similarly, it is noted that oxide layers often include additional elements in addition to silicon dioxide (SiO.sub.2)”, the third layer 205 is sufficiently disclosed and/or embodied as nitride/nitrogen and/or “SiN” doped with carbon, while layer 206 is disclosed as oxide/oxygen and/or “SiO2” doped with carbon].
Claim 10 Yoshida in view of Song, Kim [84], and Kim [21] as shown above the method of claim 1, wherein depositing the third spacer layer comprises depositing a layer of dielectric material comprising a concentration of carbon atoms and a concentration of carbon atoms in the first spacer layer [sufficiently disclosed Yoshida Paragraph 0032 “a multilayer spacer structure of oxide/nitride/oxide layers 204/205/206” and “It is also noted that nitride layers often include additional elements such as carbon (C), boron (B), oxygen (O), and/or other additives in addition to silicon nitride (SiN). Similarly, it is noted that oxide layers often include additional elements in addition to silicon dioxide (SiO.sub.2)”].
Yoshida in view of Song, Kim [84], and Kim [21] does not explicitly teach the layer of dielectric material comprising the concentration of carbon atoms is lower than the concentration of carbon atoms in the first spacer layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Song, Kim [84], and Kim [21] such that ‘the layer of dielectric material comprising the concentration of carbon atoms is lower than the concentration of carbon atoms in the first spacer layer’.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the result effective variable of etch selectivity and/or dielectric constant [See MPEP 2144.05II] and/or so that the third spacer layer is not removed by etching processes selective to carbon while the first spacer can be removed by etching processes selective to carbon.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Song, Kim [84], and Kim [21] as shown above, and in further view of US 20130164940 A1 Raley et al hereafter “Raley”.
Claim 4 Yoshida in view of Song, Kim [84], and Kim [21] The method of claim 1,
Wherein the second spacer layer comprises oxide before removing [Yoshida “oxide” and/or “SiO2”Paragraph 0032].
Yoshida in view of Song, Kim [84], and Kim [21] wherein removing the second spacer layer comprises oxidizing the second spacer layer.
Raley teaches a spacer removal process [fig. 4] comprising exposing the spacer to an oxidizing solution [410 fig. 4] and etching [420 and/or 430 fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song, Kim [84], and Kim [21] in further view of Raley such that “removing the second spacer layer comprises oxidizing the second spacer layer”.
A person of ordinary skill in the art would have been motivated to make this modification to enable subsequent etch processes selective to oxide and/or achieve an etch selectivity closer to that of oxide when there an insufficient concentration of oxide [Disclosed with sufficient specificity Raley Paragraph 0006 “The spacer etch process sequence may include oxidizing an exposed surface of the spacer material to form a spacer oxidation layer, performing a first etching process to anisotropically remove the spacer oxidation layer from the spacer material at the substrate region on the substrate and the spacer material at the capping region of the gate structure, and performing a second etching process to selectively remove the spacer material”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining etching processes for the purpose of selectively etching a layer comprising oxide.
Claim 5 Yoshida in view of Song, Kim [84], Kim [21], and Raley teach as shown above the method of claim 4, wherein removing the second spacer layer comprises performing an etch process on the oxidized second spacer layer [Yoshida fig. 2E-2F met in view Raley of 410-430 fig. 4].
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Song, Kim [84], and Kim [21] as shown above, and in further view of US 20180151706 A1 Lin et al hereafter “Lin”.
Claim 6 Yoshida in view of Song, Kim [84], and Kim [21] teach as shown above the method of claim 1
Does not teach performing a doping process on the first spacer layer after removing the second spacer layer.
Lin teaches a carbon-treatment and/or doping process of a spacer layer [sufficiently disclosed paragraph 0055 “Carbon treatment 101 may implant carbon in the first gate spacer 80” and “carbon treatment 101 may further cause the doping of the dummy dielectric with carbon ”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song, Kim [84], and Kim [21] in further view of Lin such that “a doping process on the first spacer layer after removing the second spacer layer” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to adjust the etch selectivity of the gate spacer, to strength gate spacer for subsequent processes [sufficiently disclosed paragraph 0055 “Carbon treatment 101 may help strengthen the first gate spacer 80 by providing the carbon-doped gate spacer 80B with increased etch resistivity” and “in some embodiments, carbon treatment 101 may further cause the doping of the dummy dielectric 58 with carbon and also reduce an etch rate of the dummy dielectric 58 in subsequent process steps”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is processes of forming a gate spacer/dielectric layer.
Claim 7 Yoshida in view of Song, Kim [84], and Kim [21] teach as shown above the method of claim 1,
Yoshida in view of Song, Kim [84], and Kim [21] does not teach performing an annealing process on the first spacer layer after removing the second spacer layer.
Lin teaches performing an annealing process on a spacer layer [sufficiently disclosed paragraph 0075].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song, Kim [84], and Kim [21] in further view of Lin such that “performing an annealing process on the first spacer layer after removing the second spacer layer” occurs.
A person of ordinary skill in the art would have been motivated to make this modification to achieve a uniform and/or diffuse dopant profile across the spacer layer [sufficiently disclosed paragraph 0075 Lin].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is processes of forming a gate spacer/dielectric layer.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kim [21].
Claim 11 Yoshida A method, comprising:
forming a silicon structure (112 and 122 fig. 2A) on a nanostructured layer (114 fig. 2A) on a substrate (116 fig. 2A);
depositing an inner spacer layer (204 fig. 2A) with a first dielectric constant [necessarily met as it is a property of all materials] on the silicon structure;
depositing a sacrificial spacer layer (206 fig. 2A) on the inner spacer layer [sufficiently illustrated fig. 2A];
forming a source/drain (S/D) region (172 fig. 2I) on the substrate;
removing the sacrificial spacer layer [Step 2E-2F];
depositing, on the inner spacer layer and on the S/D region, an outer spacer layer [205 fig. 2A] with a second dielectric [necessarily met as it is a property of all materials] constant higher than the first dielectric constant [sufficiently disclosed “SiO2” Silicon Dioxide and “SiN” Silicon nitride Paragraph 0032; Silicon dioxide has relative electrical permittivity of approximately 3.79-4.5 and Silicon nitride 7.9-8.1 at room temperature]; and
replacing the silicon structure with a gate structure (276 and 274 fig. 2O) surrounding the nanostructured layer [sufficiently illustrated fig. 2K-2O].
Yoshida does not explicitly teach the silicon structure is polysilicon.
Kim [21] teaches a gate replacement/dummy structure 115 [fig. 8] comprising polysilicon [Paragraph 0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in further view of Kim [21] such that the silicon structure is “polysilicon”.
A person of ordinary skill in the art would have been motivated to make this modification as selection of a known material for its known material properties is prima facie type obviousness [See MPEP 2144.07]. In this case it is the etch-selectivity of polysilicon and/or is function as a good dummy/replacement gate structure.
Claim 12 Yoshida in view of Kim [21] teaches as shown above the method of claim 11, wherein depositing the inner spacer layer comprises depositing a dielectric material comprising a concentration of carbon atoms [sufficiently disclosed “Carbon” Yoshida Paragraph 0032] is higher than a concentration of nitrogen atoms [sufficiently disclosed as SiO doped with Carbon Paragraph 0032 as no concentration of nitrogen is disclosed and/or a concentration of approximately 0%].
Alternativity, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Kim [21] such that “a dielectric material comprising a concentration of carbon is higher than a concentration of nitrogen atoms”.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of resulting affected material property of the etch selectivity and/or dielectric constant [See MPEP 2144.05II] and/or to enable etching of the layer to be selective to carbon more than that of nitrogen.
Claim 13 Yoshida in view of Kim [21] as shown above the method of claim 11, wherein depositing the outer spacer layer comprises depositing a dielectric material comprising a concentration of nitrogen atoms [sufficiently disclosed “SiN” Yoshida Paragraph 0032] and a concentration of carbon atoms [sufficiently disclosed “Carbon” Yoshida Paragraph 0032].
Yoshida in view of Kim [21] does not teach the concentration of nitrogen atoms higher than the concentration of carbon atoms.
it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Kim such that ‘the concentration of nitrogen atoms higher than the concentration of carbon atoms’.
A person of ordinary skill in the art would have been motivated to make this modification to as a part of routine optimization of resulting affected material property of the etch selectivity and/or dielectric constant [See MPEP 2144.05II] and/or to enable etching of the layer to be selective to nitrogen more than that of carbon.
Claim 14 Yoshida in view of Kim [21] as shown above the method of claim 11, wherein
The sacrificial spacer layer comprises oxide before removal [Sufficiently disclosed “SiO2” Paragraph 0032].
Yoshida in view of Kim [21] does not teach removing the sacrificial spacer layer comprises exposing the sacrificial spacer layer to an oxidizing solution.
Raley teaches a spacer removal process [fig. 4] comprising exposing the spacer to an oxidizing solution [410 fig. 4, the material solutions and/or solvents are sufficiently disclosed paragraph 0040, wherein solution includes the meaning but is not limited to “a homogenous mixture formed by mixing one solid, liquid, or gaseous substance with another” [Merriam-webster]] and etching [420 and/or 430 fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Kim [21] in further view of Raley such that “removing the sacrificial spacer layer comprises exposing the sacrificial spacer layer to an oxidizing solution”.
A person of ordinary skill in the art would have been motivated to make this modification to enable subsequent etch processes selective to oxide and/or achieve an etch selectivity closer to that of oxide when there an insufficient concentration of oxide [Disclosed with sufficient specificity Raley Paragraph 0006 “The spacer etch process sequence may include oxidizing an exposed surface of the spacer material to form a spacer oxidation layer, performing a first etching process to anisotropically remove the spacer oxidation layer from the spacer material at the substrate region on the substrate and the spacer material at the capping region of the gate structure, and performing a second etching process to selectively remove the spacer material”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining etching processes for the purpose of selectively etching a layer comprising oxide.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view and Kim [21] as shown above and in further view of US 9390981 B1 Basker et al hereafter “Basker”.
Claim 15 Yoshida in view of Kim [21] teaches as shown above the method of claim 11,
Yoshida in view of Kim [21] does not teach comprising forming an isolation layer between the S/D region and the substrate.
Basker teaches forming an isolation layer (202 fig. 22) between a S/D region (212 fig. 22) and the substrate (201 fig. 22) and explicitly state such formation processes are well known within the art [column 6 lines 25-30].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Kim [21] in further view of Basker such that “an isolation layer between the S/D region and the substrate” is formed.
A person of ordinary skill in the art would have been motivated to make this modification to isolate the S/D region from the substrate and/or prevent shorting between a transistor and adjacent devices on the substrate.
Additionally combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this is processes to from a wafer and/or base structure for the manufacturing of a transistor device.
Claim 16 Yoshida in view of Kim [21] teach as shown above the method of claim 11.
Yoshida in view of Kim [21] does no teach comprising forming a contact structure in the S/D region through the outer spacer layer.
Basker teaches a contact structure (comprising 281, 271, and 214 fig. 22) in a S/D region (213 and 212 fig. 22) [“in” is met as at least 214 penetrates into 213 the source drain structure, sufficiently illustrated fig. 22] through an outer spacer layer (233 and/or 232 fig. 22, meet under MPEP 2112.01 it is compositionally and/or structurally the same as disclosed and/or claimed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Kim [21] in further view of Basker such that “a contact structure in the S/D region through the outer spacer layer” is formed.
A person of ordinary skill in the art would have been motivated to make this modification to electrically address the source/drain structure of the transistor.
Additionally combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case it is processes to form an addressable transistor structure.
Claims 21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Song and Kim [21].
Claim 21 Yoshida teaches a method, comprising:
forming a silicon structure (122 fig. 2A) on a substrate (116 fig. 2A);
depositing, on the silicon structure, a first spacer layer (204 fig. 2A) with a concentration of carbon atoms higher than a concentration of nitrogen atoms [disclosed with sufficient specificity Paragraph 0032 in the embodiment of “SiO” doped with Carbon, wherein it has a concentration of Carbon and no and/or a concentration of approximately 0 is disclosed for nitrogen];
depositing a sacrificial spacer layer (206 fig. 2A) on the first spacer layer;
growing an epitaxial structure (172 fig. 2, disclosed Paragraph 0018 “the source and drain regions are formed as epitaxial growth regions”) in the substrate [sufficiently illustrated fig. 2I in the same manner/sense as illustrated in the figures of the instant application];
removing the sacrificial spacer layer [illustrated fig. 2E-2F];
depositing, on the first spacer layer, a second spacer layer (205 fig. 2A) with a concentration of carbon atoms (an embodiment of a doped “Carbon” concentration is sufficiently disclosed paragraph 0032);
and replacing the silicon structure with a gate structure (274 and 276 fig. 2O)[illustrated fig. 2K-2O].
Yoshida does not teach depositing, on the epitaxial structure, the second spacer layer; nor
the second spacer layer with the concentration of carbon atoms lower than the concentration of carbon atoms in the first spacer layer.
Song teaches depositing a first spacer layer (220 fig. 14);
depositing a second spacer layer (230 fig. 14) on the first spacer layer;
forming a source/drain (S/D) region (240 fig. 16) on a substrate (200 fig. 17);
removing the second spacer layer [illustrated fig. 16-17];
depositing a third spacer layer (261 fig. 18) on the first spacer layer and on the S/D region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song such that “depositing, on the epitaxial structure, the second spacer layer” occurs wherein the epitaxial structure is a source/drain.
A person of ordinary skill in the art would have been motivated to make this modification to “influencing the final electrical performance” and/or “achieving the effect of effectively reducing the parasitic capacitance between a contact hole and the gate” [Paragraph 0085-0086 Song]
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is methods for forming a gate spacer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Song such that ‘the second spacer layer with the concentration of carbon atoms lower than the concentration of carbon atoms in the first spacer layer’.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the result effective variable of etch selectivity and/or dielectric constant [See MPEP 2144.05II] and/or so that the third spacer layer is not removed by etching processes selective to carbon while the first spacer can be removed by etching processes selective to carbon.
Kim [21] teaches a gate replacement/dummy structure 115 [fig. 8] comprising polysilicon [Paragraph 0094].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song in further view of Kim [21] such that the silicon structure is “polysilicon”.
A person of ordinary skill in the art would have been motivated to make this modification as selection of a known material for its known material properties is prima facie type obviousness [See MPEP 2144.07]. In this case it is the etch-selectivity of polysilicon and/or is function as a good dummy/replacement gate structure.
Claim 23 Yoshida in view of Song and Kim [21] teach as shown above the method of claim 21, wherein depositing the second spacer layer comprises depositing the second spacer layer with a concentration of nitrogen atoms higher than a concentration of nitrogen atoms in the first spacer layer [disclosed with sufficient specificity paragraph 0032 Yoshida wherein the first spacer layer is embodied as “SiO” doped with carbon and the second spacer layer is embodied as “SiN” doped with carbon, SiN has a higher concentration of SiO, in view of Nitride not being disclosed as a dopant for the first spacer layer].
Claim 24 Yoshida in view of Song and Kim [21] The method of claim 21, wherein depositing the second spacer layer comprises:
depositing a first layer portion on the first spacer layer with a first thickness [sufficiently illustrated fig. 2A]; and
depositing a second layer portion on a top surface of the epitaxial structure [met in view of modification of Song fig. 8] with a second thickness [illustrated Yoshida fig. 2A and Song fig. 8]
Yoshida in view Song and Kim [21] does not teach the second thickness less than the first thickness as shown above.
Song teaches the second thickness less than the first thickness [fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Yoshida in view of Song and Kim [21] such that “the second thickness less than the first thickness”.
A person of ordinary skill in the art would have been motivated to make this modification to protect the underlying layers from subsequent etch steps on the second spacer layer and/or as a part of routine optimization of the time it takes to independently etch the first and second layers given the materials respective selective etch rates and the amount of insulation provided given their respective dielectric constants around the gate structure [see MPEP 2144.05II].
Additional combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case they are methods for forming a multi-layer gate spacers.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Song and Kim [21] as shown above and in further view of Raley.
Claim 22 Yoshida in view of Song and Kim [21] The method of claim 21,
The sacrificial spacer layer comprises oxide before removal [Sufficiently disclosed “SiO2” Paragraph 0032].
Yoshida in view of Song and Kim [21] does not teach removing the sacrificial spacer layer comprises exposing the sacrificial spacer layer to an oxidizing solution.
Raley teaches a spacer removal process [fig. 4] comprising exposing the spacer to an oxidizing solution [410 fig. 4, the material solutions and/or solvents are sufficiently disclosed paragraph 0040, wherein solution includes the meaning but is not limited to “a homogenous mixture formed by mixing one solid, liquid, or gaseous substance with another” [Merriam-webster]] and etching [420 and/or 430 fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Song and Kim [21] in further view of Raley such that “removing the sacrificial spacer layer comprises exposing the sacrificial spacer layer to an oxidizing solution”.
A person of ordinary skill in the art would have been motivated to make this modification to enable subsequent etch processes selective to oxide and/or achieve an etch selectivity closer to that of oxide when there an insufficient concentration of oxide [Disclosed with sufficient specificity Raley Paragraph 0006 “The spacer etch process sequence may include oxidizing an exposed surface of the spacer material to form a spacer oxidation layer, performing a first etching process to anisotropically remove the spacer oxidation layer from the spacer material at the substrate region on the substrate and the spacer material at the capping region of the gate structure, and performing a second etching process to selectively remove the spacer material”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining etching processes for the purpose of selectively etching a layer comprising oxide.
Conclusion
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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